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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id c23-20020a9d6c97000000b006c619f17669sm2733614otr.74.2023.10.26.11.35.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Oct 2023 11:35:02 -0700 (PDT) Received: (nullmailer pid 4157785 invoked by uid 1000); Thu, 26 Oct 2023 18:35:01 -0000 Date: Thu, 26 Oct 2023 13:35:01 -0500 From: Rob Herring To: Niklas Cassel Cc: Conor Dooley , Niklas Cassel , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue , Damien Le Moal , Sebastian Reichel , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-rockchip@lists.infradead.org" Subject: Re: [PATCH v2 1/4] dt-bindings: PCI: dwc: rockchip: Add atu property Message-ID: <20231026183501.GB4122054-robh@kernel.org> References: <20231024151014.240695-1-nks@flawful.org> <20231024151014.240695-2-nks@flawful.org> <20231024-zoology-preteen-5627e1125ae0@spud> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Oct 25, 2023 at 08:02:32PM +0000, Niklas Cassel wrote: > Hello Conor, > > On Tue, Oct 24, 2023 at 05:29:28PM +0100, Conor Dooley wrote: > > On Tue, Oct 24, 2023 at 05:10:08PM +0200, Niklas Cassel wrote: > > > From: Niklas Cassel > > > > > > Even though rockchip-dw-pcie.yaml inherits snps,dw-pcie.yaml > > > using: > > > > > > allOf: > > > - $ref: /schemas/pci/snps,dw-pcie.yaml# > > > > > > and snps,dw-pcie.yaml does have the atu property defined, in order to be > > > able to use this property, while still making sure 'make CHECK_DTBS=y' > > > pass, we need to add this property to rockchip-dw-pcie.yaml. > > > > > > Signed-off-by: Niklas Cassel > > > --- > > > Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 4 ++++ > > > 1 file changed, 4 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > > index 1ae8dcfa072c..229f8608c535 100644 > > > --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > > +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > > @@ -29,16 +29,20 @@ properties: > > > - const: rockchip,rk3568-pcie > > > > > > reg: > > > + minItems: 3 > > > items: > > > - description: Data Bus Interface (DBI) registers > > > - description: Rockchip designed configuration registers > > > - description: Config registers > > > + - description: iATU registers > > > > Is this extra register only for the ..88 or for the ..68 and for the > > ..88 models? > > Looking at the rk3568 Technical Reference Manual (TRM): > https://dl.radxa.com/rock3/docs/hw/datasheet/Rockchip%20RK3568%20TRM%20Part2%20V1.1-20210301.pdf > > The iATU register register range exists for all 3 PCIe controllers > found on the rk3568. > > This register range is currently not defined in the rk3568.dtsi, so the driver > will currently use the default register offset (which is correct), but with > the driver fallback register size that is only big enough to cover 8 inbound > and 8 outbound iATUs (internal Address Translation Units). We should probably make the driver smarter instead or in addition. We have the DBI size, Just make atu_size = dbi_size - DEFAULT_DBI_ATU_OFFSET. > According to the TRM, all three PCIe controllers found on the rk3568 have > 16 inbound iATUs and 16 outbound iATUs, so if someone wants to be able to > make use of all the iATUs on the rk3568, they will need to add "atu" to > rk3568.dtsi. At least for host side, the number of regions used is based on ranges. You'd be hard pressed to need more than 8. That or no h/w with 16 is probably why I said 8 was enough at the time. Rob