From: Rob Herring <robh@kernel.org>
To: Conor Dooley <conor@kernel.org>
Cc: Emil Renner Berthing <emil.renner.berthing@canonical.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>
Subject: Re: [PATCH 1/4] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
Date: Fri, 27 Oct 2023 13:22:36 -0500 [thread overview]
Message-ID: <20231027182236.GA2853373-robh@kernel.org> (raw)
In-Reply-To: <20231026-paycheck-equation-b0f1a1191bf2@spud>
On Thu, Oct 26, 2023 at 02:10:37PM +0100, Conor Dooley wrote:
> On Wed, Oct 25, 2023 at 11:56:37AM -0700, Emil Renner Berthing wrote:
> > This cache controller is also used on the StarFive JH7100 SoC.
> > Unfortunately it needs a quirk to work properly, so add dedicated
> > compatible string to be able to match it.
> >
> > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Did you want me to pick this up? Or you or Palmer will?
Rob
next prev parent reply other threads:[~2023-10-27 18:22 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-25 18:56 [PATCH 1/4] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible Emil Renner Berthing
2023-10-26 13:10 ` Conor Dooley
2023-10-27 18:22 ` Rob Herring [this message]
2023-10-27 18:38 ` Conor Dooley
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