From: Conor Dooley <conor@kernel.org>
To: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Subject: Re: [PATCH v2 0/2] soc: sifive: ccache: Add StarFive JH7100 support
Date: Wed, 1 Nov 2023 11:52:55 +0000 [thread overview]
Message-ID: <20231101-random-overlord-1315a03183fc@spud> (raw)
In-Reply-To: <20231031141444.53426-1-emil.renner.berthing@canonical.com>
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On Tue, Oct 31, 2023 at 03:14:42PM +0100, Emil Renner Berthing wrote:
> This series adds support for the StarFive JH7100 SoC to the SiFive cache
> controller driver. The JH7100 was a "development version" of the JH7110
> used on the BeagleV Starlight and VisionFive V1 boards. It has
> non-coherent peripheral DMAs but was designed before the standard RISC-V
> Zicbom extension, so it neeeds support in this driver for non-standard
> cache management.
>
> Since v1:
> - Fix email threading, hopefully.
> - Drop sifive,ccache-ops device tree property and just match on the
> compatible. (Conor)
I'll grab these after the mw, presuming nothing comes up in the interim.
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next prev parent reply other threads:[~2023-11-01 11:53 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-31 14:14 [PATCH v2 0/2] soc: sifive: ccache: Add StarFive JH7100 support Emil Renner Berthing
2023-10-31 14:14 ` [PATCH v2 1/2] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible Emil Renner Berthing
2023-10-31 14:14 ` [PATCH v2 2/2] soc: sifive: ccache: Add StarFive JH7100 support Emil Renner Berthing
2023-11-03 15:53 ` Conor Dooley
2023-11-01 11:52 ` Conor Dooley [this message]
2023-11-22 11:59 ` [PATCH v2 0/2] " Conor Dooley
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