From: Manivannan Sadhasivam <mani@kernel.org>
To: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Cc: agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, vireshk@kernel.org, nm@ti.com,
sboyd@kernel.org, lpieralisi@kernel.org, kw@linux.com,
robh@kernel.org, bhelgaas@google.com, rafael@kernel.org,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, quic_vbadigan@quicinc.com,
quic_nitegupt@quicinc.com, quic_skananth@quicinc.com,
quic_ramkri@quicinc.com, quic_parass@quicinc.com
Subject: Re: [PATCH v5 5/5] PCI: qcom: Add OPP support to scale performance state of power domain
Date: Wed, 1 Nov 2023 12:03:23 +0530 [thread overview]
Message-ID: <20231101063323.GH2897@thinkpad> (raw)
In-Reply-To: <1694066433-8677-6-git-send-email-quic_krichai@quicinc.com>
On Thu, Sep 07, 2023 at 11:30:33AM +0530, Krishna chaitanya chundru wrote:
> While scaling the interconnect clocks based on PCIe link speed, it is also
> mandatory to scale the power domain performance state so that the SoC can
> run under optimum power conditions.
>
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 58 ++++++++++++++++++++++++++++------
> 1 file changed, 49 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index ca6350b..1817e96 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -22,6 +22,7 @@
> #include <linux/of.h>
> #include <linux/of_gpio.h>
> #include <linux/pci.h>
> +#include <linux/pm_opp.h>
> #include <linux/pm_runtime.h>
> #include <linux/platform_device.h>
> #include <linux/phy/pcie.h>
> @@ -240,6 +241,7 @@ struct qcom_pcie {
> const struct qcom_pcie_cfg *cfg;
> struct dentry *debugfs;
> bool suspended;
> + bool opp_supported;
> };
>
> #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
> @@ -1357,14 +1359,13 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
> return 0;
> }
>
> -static int qcom_pcie_icc_update(struct qcom_pcie *pcie)
> +static int qcom_pcie_icc_opp_update(struct qcom_pcie *pcie)
> {
> struct dw_pcie *pci = pcie->pci;
> + struct dev_pm_opp *opp;
> u32 offset, status, bw;
> int speed, width;
> -
> - if (!pcie->icc_mem)
> - return 0;
> + int ret;
>
> offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
> @@ -1391,7 +1392,21 @@ static int qcom_pcie_icc_update(struct qcom_pcie *pcie)
> break;
> }
>
> - return icc_set_bw(pcie->icc_mem, 0, width * bw);
> + if (pcie->opp_supported) {
> + opp = dev_pm_opp_find_level_exact(pci->dev, speed);
> + if (!IS_ERR(opp)) {
> + ret = dev_pm_opp_set_opp(pci->dev, opp);
> + if (ret)
> + dev_err(pci->dev, "Failed to set opp: level %d ret %d\n",
> + dev_pm_opp_get_level(opp), ret);
> + dev_pm_opp_put(opp);
> + }
> + }
> +
> + if (pcie->icc_mem)
> + ret = icc_set_bw(pcie->icc_mem, 0, width * bw);
I think you should tie interconnect scaling with OPP as suggested by Viresh,
since you are updating both OPP and BW at the same time.
- Mani
> +
> + return ret;
> }
>
> static int qcom_pcie_link_transition_count(struct seq_file *s, void *data)
> @@ -1434,8 +1449,10 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie)
> static int qcom_pcie_probe(struct platform_device *pdev)
> {
> const struct qcom_pcie_cfg *pcie_cfg;
> + unsigned long max_level = INT_MAX;
> struct device *dev = &pdev->dev;
> struct qcom_pcie *pcie;
> + struct dev_pm_opp *opp;
> struct dw_pcie_rp *pp;
> struct resource *res;
> struct dw_pcie *pci;
> @@ -1506,6 +1523,27 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> if (ret)
> goto err_pm_runtime_put;
>
> + /* OPP table is optional */
> + ret = devm_pm_opp_of_add_table(dev);
> + if (ret && ret != -ENODEV) {
> + dev_err_probe(dev, ret, "Failed to add OPP table\n");
> + goto err_pm_runtime_put;
> + }
> +
> + /* vote for max level in the opp table if opp table is present */
> + if (ret != -ENODEV) {
> + opp = dev_pm_opp_find_level_floor(dev, &max_level);
> + if (!IS_ERR(opp)) {
> + ret = dev_pm_opp_set_opp(dev, opp);
> + if (ret)
> + dev_err_probe(pci->dev, ret,
> + "Failed to set opp: level %d\n",
> + dev_pm_opp_get_level(opp));
> + dev_pm_opp_put(opp);
> + }
> + pcie->opp_supported = true;
> + }
> +
> ret = pcie->cfg->ops->get_resources(pcie);
> if (ret)
> goto err_pm_runtime_put;
> @@ -1524,9 +1562,9 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> goto err_phy_exit;
> }
>
> - ret = qcom_pcie_icc_update(pcie);
> + ret = qcom_pcie_icc_opp_update(pcie);
> if (ret)
> - dev_err(dev, "failed to update interconnect bandwidth: %d\n",
> + dev_err(dev, "failed to update interconnect bandwidth/opp: %d\n",
> ret);
>
> if (pcie->mhi)
> @@ -1575,6 +1613,8 @@ static int qcom_pcie_suspend_noirq(struct device *dev)
> */
> if (!dw_pcie_link_up(pcie->pci)) {
> qcom_pcie_host_deinit(&pcie->pci->pp);
> + if (pcie->opp_supported)
> + dev_pm_opp_set_opp(dev, NULL);
> pcie->suspended = true;
> }
>
> @@ -1594,9 +1634,9 @@ static int qcom_pcie_resume_noirq(struct device *dev)
> pcie->suspended = false;
> }
>
> - ret = qcom_pcie_icc_update(pcie);
> + ret = qcom_pcie_icc_opp_update(pcie);
> if (ret)
> - dev_err(dev, "failed to update interconnect bandwidth: %d\n",
> + dev_err(dev, "failed to update interconnect bandwidth/opp: %d\n",
> ret);
>
> return 0;
> --
> 2.7.4
>
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2023-11-01 6:33 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-07 6:00 [PATCH v5 0/5] PCI: qcom: Add support for OPP Krishna chaitanya chundru
2023-09-07 6:00 ` [PATCH v5 1/5] dt-bindings: pci: qcom: Add opp table Krishna chaitanya chundru
2023-09-07 6:00 ` [PATCH v5 2/5] arm64: dts: qcom: sm8450: Add opp table support to PCIe Krishna chaitanya chundru
2023-09-07 9:04 ` Konrad Dybcio
2023-09-07 9:56 ` Krishna Chaitanya Chundru
2023-09-07 10:28 ` Konrad Dybcio
2023-09-28 18:38 ` Manivannan Sadhasivam
2023-10-05 8:52 ` Krishna Chaitanya Chundru
2023-09-07 6:00 ` [PATCH v5 3/5] opp: Add dev_pm_opp_find_level_floor() Krishna chaitanya chundru
2023-09-27 7:14 ` Viresh Kumar
2023-09-28 3:24 ` Krishna Chaitanya Chundru
2023-09-28 3:35 ` Krishna Chaitanya Chundru
2023-09-07 6:00 ` [PATCH v5 4/5] PCI: qcom: Return error from 'qcom_pcie_icc_update' Krishna chaitanya chundru
2023-11-01 6:30 ` Manivannan Sadhasivam
2023-09-07 6:00 ` [PATCH v5 5/5] PCI: qcom: Add OPP support to scale performance state of power domain Krishna chaitanya chundru
[not found] ` <20230927065324.w73ae326vs5ftlfo@vireshk-i7>
[not found] ` <f7a5ac7f-2857-8d30-e29c-f64c2c5f1330@quicinc.com>
2023-09-28 6:31 ` Viresh Kumar
2023-11-01 6:33 ` Manivannan Sadhasivam [this message]
2023-11-01 22:17 ` Bjorn Helgaas
2023-11-02 5:30 ` Viresh Kumar
2023-11-02 12:09 ` Bjorn Helgaas
2023-11-03 5:12 ` Viresh Kumar
2023-11-08 2:32 ` Krishna Chaitanya Chundru
2024-01-08 13:19 ` Krishna Chaitanya Chundru
2024-01-10 6:57 ` Viresh Kumar
2024-01-10 7:12 ` Krishna Chaitanya Chundru
2024-01-10 7:38 ` Viresh Kumar
2024-01-10 12:58 ` Krishna Chaitanya Chundru
2024-01-11 3:32 ` Viresh Kumar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231101063323.GH2897@thinkpad \
--to=mani@kernel.org \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=bhelgaas@google.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=nm@ti.com \
--cc=quic_krichai@quicinc.com \
--cc=quic_nitegupt@quicinc.com \
--cc=quic_parass@quicinc.com \
--cc=quic_ramkri@quicinc.com \
--cc=quic_skananth@quicinc.com \
--cc=quic_vbadigan@quicinc.com \
--cc=rafael@kernel.org \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=vireshk@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).