[PATCH 0/4] dmaengine: fsl-edma: integrate TCD64 support for 64bit physical address

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* [PATCH 0/4] dmaengine: fsl-edma: integrate TCD64 support for 64bit physical address
@ 2023-11-09 21:20 Frank Li
  2023-11-09 21:20 ` [PATCH 1/4] dmaengine: fsl-edma: involve help macro fsl_edma_set(get)_tcd() Frank Li
                   ` (3 more replies)
  0 siblings, 4 replies; 15+ messages in thread
From: Frank Li @ 2023-11-09 21:20 UTC (permalink / raw)
  To: frank.li
  Cc: devicetree, dmaengine, imx, joy.zou, krzysztof.kozlowski+dt,
	linux-kernel, peng.fan, robh+dt, shenwei.wang, vkoul

first 2 patch is prepare, No function change.
3rd patch is dt-bind doc
4rd patch is actuall support TCD64

Frank Li (4):
  dmaengine: fsl-edma: involve help macro fsl_edma_set(get)_tcd()
  dmaengine: fsl-edma: add address for channel mux register in
    fsl_edma_chan
  dt-bindings: fsl-dma: fsl-edma: add fsl,imx95-edma5 compatible string
  dmaengine: fsl-edma: integrate TCD64 support for i.MX95

 .../devicetree/bindings/dma/fsl,edma.yaml     |   2 +
 drivers/dma/fsl-edma-common.c                 |  85 ++++++------
 drivers/dma/fsl-edma-common.h                 | 126 ++++++++++++++++--
 drivers/dma/fsl-edma-main.c                   |  17 +++
 4 files changed, 178 insertions(+), 52 deletions(-)

-- 
2.34.1


^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCH 1/4] dmaengine: fsl-edma: involve help macro fsl_edma_set(get)_tcd()
  2023-11-09 21:20 [PATCH 0/4] dmaengine: fsl-edma: integrate TCD64 support for 64bit physical address Frank Li
@ 2023-11-09 21:20 ` Frank Li
  2023-11-09 21:20 ` [PATCH 2/4] dmaengine: fsl-edma: add address for channel mux register in fsl_edma_chan Frank Li
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2023-11-09 21:20 UTC (permalink / raw)
  To: frank.li
  Cc: devicetree, dmaengine, imx, joy.zou, krzysztof.kozlowski+dt,
	linux-kernel, peng.fan, robh+dt, shenwei.wang, vkoul

Using help macro fsl_edma_set(get)_tcd() to handle difference field size.
This is not function change and prepare for 64bit tcd in imx95.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/dma/fsl-edma-common.c | 61 ++++++++++++++++++-----------------
 drivers/dma/fsl-edma-common.h | 20 ++++++++++++
 2 files changed, 51 insertions(+), 30 deletions(-)

diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 6a3abe5b17908..1cd9cf51b16eb 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -358,10 +358,10 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
 
 	/* calculate the total size in this desc */
 	for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) {
-		nbytes = le32_to_cpu(edesc->tcd[i].vtcd->nbytes);
+		nbytes = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, nbytes);
 		if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE | EDMA_V3_TCD_NBYTES_SMLOE))
 			nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes);
-		len += nbytes * le16_to_cpu(edesc->tcd[i].vtcd->biter);
+		len += nbytes * fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, biter);
 	}
 
 	if (!in_progress)
@@ -374,16 +374,16 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
 
 	/* figure out the finished and calculate the residue */
 	for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
-		nbytes = le32_to_cpu(edesc->tcd[i].vtcd->nbytes);
+		nbytes = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, nbytes);
 		if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE | EDMA_V3_TCD_NBYTES_SMLOE))
 			nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes);
 
-		size = nbytes * le16_to_cpu(edesc->tcd[i].vtcd->biter);
+		size = nbytes * fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, biter);
 
 		if (dir == DMA_MEM_TO_DEV)
-			dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr);
+			dma_addr = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, saddr);
 		else
-			dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr);
+			dma_addr = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, daddr);
 
 		len -= size;
 		if (cur_addr >= dma_addr && cur_addr < dma_addr + size) {
@@ -439,26 +439,26 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
 	 */
 	edma_write_tcdreg(fsl_chan, 0, csr);
 
-	edma_write_tcdreg(fsl_chan, tcd->saddr, saddr);
-	edma_write_tcdreg(fsl_chan, tcd->daddr, daddr);
+	edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, saddr), saddr);
+	edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, daddr), daddr);
 
-	edma_write_tcdreg(fsl_chan, tcd->attr, attr);
-	edma_write_tcdreg(fsl_chan, tcd->soff, soff);
+	edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, attr), attr);
+	edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, soff), soff);
 
-	edma_write_tcdreg(fsl_chan, tcd->nbytes, nbytes);
-	edma_write_tcdreg(fsl_chan, tcd->slast, slast);
+	edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, nbytes), nbytes);
+	edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, slast), slast);
 
-	edma_write_tcdreg(fsl_chan, tcd->citer, citer);
-	edma_write_tcdreg(fsl_chan, tcd->biter, biter);
-	edma_write_tcdreg(fsl_chan, tcd->doff, doff);
+	edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, citer), citer);
+	edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, biter), biter);
+	edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, doff), doff);
 
-	edma_write_tcdreg(fsl_chan, tcd->dlast_sga, dlast_sga);
+	edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, dlast_sga), dlast_sga);
 
-	csr = le16_to_cpu(tcd->csr);
+	csr = fsl_edma_get_tcd_to_cpu(fsl_chan, tcd, csr);
 
 	if (fsl_chan->is_sw) {
 		csr |= EDMA_TCD_CSR_START;
-		tcd->csr = cpu_to_le16(csr);
+		fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr);
 	}
 
 	/*
@@ -473,7 +473,7 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
 		edma_writel_chreg(fsl_chan, edma_readl_chreg(fsl_chan, ch_csr), ch_csr);
 
 
-	edma_write_tcdreg(fsl_chan, tcd->csr, csr);
+	edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, csr), csr);
 }
 
 static inline
@@ -493,12 +493,12 @@ void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan,
 	 * So we put the value in little endian in memory, waiting
 	 * for fsl_edma_set_tcd_regs doing the swap.
 	 */
-	tcd->saddr = cpu_to_le32(src);
-	tcd->daddr = cpu_to_le32(dst);
+	fsl_edma_set_tcd_to_le(fsl_chan, tcd, src, saddr);
+	fsl_edma_set_tcd_to_le(fsl_chan, tcd, dst, daddr);
 
-	tcd->attr = cpu_to_le16(attr);
+	fsl_edma_set_tcd_to_le(fsl_chan, tcd, attr, attr);
 
-	tcd->soff = cpu_to_le16(soff);
+	fsl_edma_set_tcd_to_le(fsl_chan, tcd, soff, soff);
 
 	if (fsl_chan->is_multi_fifo) {
 		/* set mloff to support multiple fifo */
@@ -515,15 +515,16 @@ void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan,
 		}
 	}
 
-	tcd->nbytes = cpu_to_le32(nbytes);
-	tcd->slast = cpu_to_le32(slast);
+	fsl_edma_set_tcd_to_le(fsl_chan, tcd, nbytes, nbytes);
+	fsl_edma_set_tcd_to_le(fsl_chan, tcd, slast, slast);
 
-	tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer));
-	tcd->doff = cpu_to_le16(doff);
+	fsl_edma_set_tcd_to_le(fsl_chan, tcd, EDMA_TCD_CITER_CITER(citer), citer);
+	fsl_edma_set_tcd_to_le(fsl_chan, tcd, doff, doff);
 
-	tcd->dlast_sga = cpu_to_le32(dlast_sga);
+	fsl_edma_set_tcd_to_le(fsl_chan, tcd, dlast_sga, dlast_sga);
+
+	fsl_edma_set_tcd_to_le(fsl_chan, tcd, EDMA_TCD_BITER_BITER(biter), biter);
 
-	tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter));
 	if (major_int)
 		csr |= EDMA_TCD_CSR_INT_MAJOR;
 
@@ -539,7 +540,7 @@ void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan,
 	if (fsl_chan->is_sw)
 		csr |= EDMA_TCD_CSR_START;
 
-	tcd->csr = cpu_to_le16(csr);
+	fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr);
 }
 
 static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan,
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index bb5221158a770..72104d775e562 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -246,6 +246,26 @@ struct fsl_edma_engine {
 	edma_writel(chan->edma, val,				\
 		   (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name))
 
+#define fsl_edma_get_tcd(_chan, _tcd, _field) ((_tcd)->_field)
+
+#define fsl_edma_le_to_cpu(x)					\
+(sizeof(x) == sizeof(u32) ? le32_to_cpu(x) : le16_to_cpu(x))
+
+#define fsl_edma_get_tcd_to_cpu(_chan, _tcd, _field)		\
+fsl_edma_le_to_cpu(fsl_edma_get_tcd(_chan, _tcd, _field))
+
+#define fsl_edma_set_tcd_to_le(_fsl_chan, _tcd, _val, _field)	\
+do {								\
+	switch (sizeof((_tcd)->_field)) {				\
+	case sizeof(u32):					\
+		(_tcd)->_field = cpu_to_le32(_val);		\
+		break;						\
+	case sizeof(u16):					\
+		(_tcd)->_field = cpu_to_le16(_val);		\
+		break;						\
+	}							\
+} while (0)
+
 /*
  * R/W functions for big- or little-endian registers:
  * The eDMA controller's endian is independent of the CPU core's endian.
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 2/4] dmaengine: fsl-edma: add address for channel mux register in fsl_edma_chan
  2023-11-09 21:20 [PATCH 0/4] dmaengine: fsl-edma: integrate TCD64 support for 64bit physical address Frank Li
  2023-11-09 21:20 ` [PATCH 1/4] dmaengine: fsl-edma: involve help macro fsl_edma_set(get)_tcd() Frank Li
@ 2023-11-09 21:20 ` Frank Li
  2023-11-09 21:20 ` [PATCH 3/4] dt-bindings: fsl-dma: fsl-edma: add fsl,imx95-edma5 compatible string Frank Li
  2023-11-09 21:20 ` [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95 Frank Li
  3 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2023-11-09 21:20 UTC (permalink / raw)
  To: frank.li
  Cc: devicetree, dmaengine, imx, joy.zou, krzysztof.kozlowski+dt,
	linux-kernel, peng.fan, robh+dt, shenwei.wang, vkoul

iMX95 move channel mux register to management page address space. This
prepare to support iMX95.

Add mux_addr in struct fsl_edma_chan. No function change.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/dma/fsl-edma-common.c | 6 +++---
 drivers/dma/fsl-edma-common.h | 3 +++
 drivers/dma/fsl-edma-main.c   | 3 +++
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 1cd9cf51b16eb..d29824ed7c80f 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -97,8 +97,8 @@ static void fsl_edma3_enable_request(struct fsl_edma_chan *fsl_chan)
 		 * ch_mux: With the exception of 0, attempts to write a value
 		 * already in use will be forced to 0.
 		 */
-		if (!edma_readl_chreg(fsl_chan, ch_mux))
-			edma_writel_chreg(fsl_chan, fsl_chan->srcid, ch_mux);
+		if (!edma_readl(fsl_chan->edma, fsl_chan->mux_addr))
+			edma_writel(fsl_chan->edma, fsl_chan->srcid, fsl_chan->mux_addr);
 	}
 
 	val = edma_readl_chreg(fsl_chan, ch_csr);
@@ -134,7 +134,7 @@ static void fsl_edma3_disable_request(struct fsl_edma_chan *fsl_chan)
 	flags = fsl_edma_drvflags(fsl_chan);
 
 	if (flags & FSL_EDMA_DRV_HAS_CHMUX)
-		edma_writel_chreg(fsl_chan, 0, ch_mux);
+		edma_writel(fsl_chan->edma, 0, fsl_chan->mux_addr);
 
 	val &= ~EDMA_V3_CH_CSR_ERQ;
 	edma_writel_chreg(fsl_chan, val, ch_csr);
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 72104d775e562..6c738c5cad118 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -145,6 +145,7 @@ struct fsl_edma_chan {
 	enum dma_data_direction		dma_dir;
 	char				chan_name[32];
 	struct fsl_edma_hw_tcd __iomem *tcd;
+	void __iomem			*mux_addr;
 	u32				real_count;
 	struct work_struct		issue_worker;
 	struct platform_device		*pdev;
@@ -206,6 +207,8 @@ struct fsl_edma_drvdata {
 	u32			chreg_off;
 	u32			chreg_space_sz;
 	u32			flags;
+	u32			mux_off;	/* channel mux register offset */
+	u32			mux_skip;	/* how much skip for each channel */
 	int			(*setup_irq)(struct platform_device *pdev,
 					     struct fsl_edma_engine *fsl_edma);
 };
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index 4635e16d7705e..8e5ddeb5e887f 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -356,6 +356,8 @@ static struct fsl_edma_drvdata imx93_data4 = {
 	.flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4,
 	.chreg_space_sz = 0x8000,
 	.chreg_off = 0x10000,
+	.mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux),
+	.mux_skip = 0x8000,
 	.setup_irq = fsl_edma3_irq_init,
 };
 
@@ -530,6 +532,7 @@ static int fsl_edma_probe(struct platform_device *pdev)
 				offsetof(struct fsl_edma3_ch_reg, tcd) : 0;
 		fsl_chan->tcd = fsl_edma->membase
 				+ i * drvdata->chreg_space_sz + drvdata->chreg_off + len;
+		fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip;
 
 		fsl_chan->pdev = pdev;
 		vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 3/4] dt-bindings: fsl-dma: fsl-edma: add fsl,imx95-edma5 compatible string
  2023-11-09 21:20 [PATCH 0/4] dmaengine: fsl-edma: integrate TCD64 support for 64bit physical address Frank Li
  2023-11-09 21:20 ` [PATCH 1/4] dmaengine: fsl-edma: involve help macro fsl_edma_set(get)_tcd() Frank Li
  2023-11-09 21:20 ` [PATCH 2/4] dmaengine: fsl-edma: add address for channel mux register in fsl_edma_chan Frank Li
@ 2023-11-09 21:20 ` Frank Li
  2023-11-10  7:56   ` Krzysztof Kozlowski
  2023-11-09 21:20 ` [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95 Frank Li
  3 siblings, 1 reply; 15+ messages in thread
From: Frank Li @ 2023-11-09 21:20 UTC (permalink / raw)
  To: frank.li
  Cc: devicetree, dmaengine, imx, joy.zou, krzysztof.kozlowski+dt,
	linux-kernel, peng.fan, robh+dt, shenwei.wang, vkoul

Add the compatible string 'fsl,imx95-edma5' to support the i.MX95's eDMA,
which features 64-bit physical address support.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 Documentation/devicetree/bindings/dma/fsl,edma.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
index 437db0c62339f..aa51d278cb67b 100644
--- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml
+++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
@@ -25,6 +25,7 @@ properties:
           - fsl,imx8qm-edma
           - fsl,imx93-edma3
           - fsl,imx93-edma4
+          - fsl,imx95-edma5
       - items:
           - const: fsl,ls1028a-edma
           - const: fsl,vf610-edma
@@ -83,6 +84,7 @@ allOf:
               - fsl,imx8qm-edma
               - fsl,imx93-edma3
               - fsl,imx93-edma4
+              - fsl,imx95-edma5
     then:
       properties:
         "#dma-cells":
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* Re: [PATCH 3/4] dt-bindings: fsl-dma: fsl-edma: add fsl,imx95-edma5 compatible string
  2023-11-09 21:20 ` [PATCH 3/4] dt-bindings: fsl-dma: fsl-edma: add fsl,imx95-edma5 compatible string Frank Li
@ 2023-11-10  7:56   ` Krzysztof Kozlowski
  0 siblings, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2023-11-10  7:56 UTC (permalink / raw)
  To: Frank Li
  Cc: devicetree, dmaengine, imx, joy.zou, krzysztof.kozlowski+dt,
	linux-kernel, peng.fan, robh+dt, shenwei.wang, vkoul

On 09/11/2023 22:20, Frank Li wrote:
> Add the compatible string 'fsl,imx95-edma5' to support the i.MX95's eDMA,
> which features 64-bit physical address support.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95
  2023-11-09 21:20 [PATCH 0/4] dmaengine: fsl-edma: integrate TCD64 support for 64bit physical address Frank Li
                   ` (2 preceding siblings ...)
  2023-11-09 21:20 ` [PATCH 3/4] dt-bindings: fsl-dma: fsl-edma: add fsl,imx95-edma5 compatible string Frank Li
@ 2023-11-09 21:20 ` Frank Li
  2023-11-10  6:09   ` kernel test robot
                     ` (3 more replies)
  3 siblings, 4 replies; 15+ messages in thread
From: Frank Li @ 2023-11-09 21:20 UTC (permalink / raw)
  To: frank.li
  Cc: devicetree, dmaengine, imx, joy.zou, krzysztof.kozlowski+dt,
	linux-kernel, peng.fan, robh+dt, shenwei.wang, vkoul

In i.MX95's edma version 5, the TCD structure is extended to support 64-bit
addresses for fields like saddr and daddr. To prevent code duplication,
employ help macros to handle the fields, as the field names remain the same
between TCD and TCD64.

Change local variables related to TCD addresses from 'u32' to 'dma_addr_t'
to accept 64-bit DMA addresses.

Change 'vtcd' type to 'void *' to avoid direct use. Use helper macros to
access the TCD fields correctly.

Call 'dma_set_mask_and_coherent(64)' when TCD64 is supported.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/dma/fsl-edma-common.c |  18 +++---
 drivers/dma/fsl-edma-common.h | 109 +++++++++++++++++++++++++++++-----
 drivers/dma/fsl-edma-main.c   |  14 +++++
 3 files changed, 119 insertions(+), 22 deletions(-)

diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index d29824ed7c80f..47ab4db3d98ec 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -426,8 +426,7 @@ enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
 	return fsl_chan->status;
 }
 
-static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
-				  struct fsl_edma_hw_tcd *tcd)
+static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, void *tcd)
 {
 	u16 csr = 0;
 
@@ -478,9 +477,9 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
 
 static inline
 void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan,
-		       struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst,
-		       u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer,
-		       u16 biter, u16 doff, u32 dlast_sga, bool major_int,
+		       struct fsl_edma_hw_tcd *tcd, dma_addr_t src, dma_addr_t dst,
+		       u16 attr, u16 soff, u32 nbytes, dma_addr_t slast, u16 citer,
+		       u16 biter, u16 doff, dma_addr_t dlast_sga, bool major_int,
 		       bool disable_req, bool enable_sg)
 {
 	struct dma_slave_config *cfg = &fsl_chan->cfg;
@@ -581,8 +580,9 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
 	dma_addr_t dma_buf_next;
 	bool major_int = true;
 	int sg_len, i;
-	u32 src_addr, dst_addr, last_sg, nbytes;
+	dma_addr_t src_addr, dst_addr, last_sg;
 	u16 soff, doff, iter;
+	u32 nbytes;
 
 	if (!is_slave_direction(direction))
 		return NULL;
@@ -654,8 +654,9 @@ struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
 	struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 	struct fsl_edma_desc *fsl_desc;
 	struct scatterlist *sg;
-	u32 src_addr, dst_addr, last_sg, nbytes;
+	dma_addr_t src_addr, dst_addr, last_sg;
 	u16 soff, doff, iter;
+	u32 nbytes;
 	int i;
 
 	if (!is_slave_direction(direction))
@@ -804,7 +805,8 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *chan)
 	struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 
 	fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev,
-				sizeof(struct fsl_edma_hw_tcd),
+				fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_TCD64 ?
+				sizeof(struct fsl_edma_hw_tcd64) : sizeof(struct fsl_edma_hw_tcd),
 				32, 0);
 	return 0;
 }
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 6c738c5cad118..5357dccdc1a40 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -87,6 +87,20 @@ struct fsl_edma_hw_tcd {
 	__le16	biter;
 };
 
+struct fsl_edma_hw_tcd64 {
+	__le64  saddr;
+	__le16  soff;
+	__le16  attr;
+	__le32  nbytes;
+	__le64  slast;
+	__le64  daddr;
+	__le64  dlast_sga;
+	__le16  doff;
+	__le16  citer;
+	__le16  csr;
+	__le16  biter;
+} __packed;
+
 struct fsl_edma3_ch_reg {
 	__le32	ch_csr;
 	__le32	ch_es;
@@ -96,7 +110,10 @@ struct fsl_edma3_ch_reg {
 	__le32	ch_mux;
 	__le32  ch_mattr; /* edma4, reserved for edma3 */
 	__le32  ch_reserved;
-	struct fsl_edma_hw_tcd tcd;
+	union {
+		struct fsl_edma_hw_tcd tcd;
+		struct fsl_edma_hw_tcd tcd64;
+	};
 } __packed;
 
 /*
@@ -125,7 +142,7 @@ struct edma_regs {
 
 struct fsl_edma_sw_tcd {
 	dma_addr_t			ptcd;
-	struct fsl_edma_hw_tcd		*vtcd;
+	void				*vtcd;
 };
 
 struct fsl_edma_chan {
@@ -144,7 +161,7 @@ struct fsl_edma_chan {
 	u32				dma_dev_size;
 	enum dma_data_direction		dma_dir;
 	char				chan_name[32];
-	struct fsl_edma_hw_tcd __iomem *tcd;
+	void __iomem			*tcd;
 	void __iomem			*mux_addr;
 	u32				real_count;
 	struct work_struct		issue_worker;
@@ -188,6 +205,7 @@ struct fsl_edma_desc {
 #define FSL_EDMA_DRV_CLEAR_DONE_E_SG	BIT(13)
 /* Need clean CHn_CSR DONE before enable TCD's MAJORELINK */
 #define FSL_EDMA_DRV_CLEAR_DONE_E_LINK	BIT(14)
+#define FSL_EDMA_DRV_TCD64		BIT(15)
 
 #define FSL_EDMA_DRV_EDMA3	(FSL_EDMA_DRV_SPLIT_REG |	\
 				 FSL_EDMA_DRV_BUS_8BYTE |	\
@@ -231,15 +249,44 @@ struct fsl_edma_engine {
 	struct fsl_edma_chan	chans[] __counted_by(n_chans);
 };
 
+#define edma_read_tcdreg_c(chan, _tcd,  __name)			\
+(sizeof(_tcd->__name) == sizeof(u64) ?				\
+	edma_readq(chan->edma, &_tcd->__name) :			\
+		((sizeof(_tcd->__name) == sizeof(u32)) ?	\
+			edma_readl(chan->edma, &_tcd->__name) :	\
+			edma_readw(chan->edma, &_tcd->__name)	\
+		))
+
 #define edma_read_tcdreg(chan, __name)				\
-(sizeof(chan->tcd->__name) == sizeof(u32) ?			\
-	edma_readl(chan->edma, &chan->tcd->__name) :		\
-	edma_readw(chan->edma, &chan->tcd->__name))
+((fsl_edma_drvflags(chan) & FSL_EDMA_DRV_TCD64) ?		\
+	edma_read_tcdreg_c(chan, ((struct fsl_edma_hw_tcd64 *)chan->tcd), __name) :		\
+	edma_read_tcdreg_c(chan, ((struct fsl_edma_hw_tcd *)chan->tcd), __name)		\
+)
 
-#define edma_write_tcdreg(chan, val, __name)			\
-(sizeof(chan->tcd->__name) == sizeof(u32) ?			\
-	edma_writel(chan->edma, (u32 __force)val, &chan->tcd->__name) :	\
-	edma_writew(chan->edma, (u16 __force)val, &chan->tcd->__name))
+#define edma_write_tcdreg_c(chan, _tcd, _val, __name)		\
+do {								\
+	switch (sizeof(_tcd->__name)) {				\
+	case sizeof(u64):					\
+		edma_writeq(chan->edma, (u64 __force)_val, &_tcd->__name);	\
+		break;						\
+	case sizeof(u32):					\
+		edma_writel(chan->edma, (u32 __force)_val, &_tcd->__name);	\
+		break;						\
+	case sizeof(u16):					\
+		edma_writew(chan->edma, (u16 __force)_val, &_tcd->__name);	\
+		break;						\
+	case sizeof(u8):					\
+		edma_writeb(chan->edma, _val, &_tcd->__name);	\
+		break;						\
+	}							\
+} while (0)
+
+#define edma_write_tcdreg(chan, val, __name)				\
+do {	if (fsl_edma_drvflags(chan) & FSL_EDMA_DRV_TCD64)		\
+		edma_write_tcdreg_c(chan, ((struct fsl_edma_hw_tcd64 *)chan->tcd), val, __name);\
+	else								\
+		edma_write_tcdreg_c(chan, ((struct fsl_edma_hw_tcd *)chan->tcd), val, __name);	\
+} while (0)
 
 #define edma_readl_chreg(chan, __name)				\
 	edma_readl(chan->edma,					\
@@ -249,17 +296,24 @@ struct fsl_edma_engine {
 	edma_writel(chan->edma, val,				\
 		   (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name))
 
-#define fsl_edma_get_tcd(_chan, _tcd, _field) ((_tcd)->_field)
+#define fsl_edma_get_tcd(_chan, _tcd, _field)			\
+(fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ? (((struct fsl_edma_hw_tcd64 *)_tcd)->_field) : \
+						 (((struct fsl_edma_hw_tcd *)_tcd)->_field))
 
 #define fsl_edma_le_to_cpu(x)					\
-(sizeof(x) == sizeof(u32) ? le32_to_cpu(x) : le16_to_cpu(x))
+(sizeof(x) == sizeof(u64) ? le64_to_cpu(x) :			\
+	(sizeof(x) == sizeof(u32) ? le32_to_cpu(x) : le16_to_cpu(x)))
+
 
 #define fsl_edma_get_tcd_to_cpu(_chan, _tcd, _field)		\
 fsl_edma_le_to_cpu(fsl_edma_get_tcd(_chan, _tcd, _field))
 
-#define fsl_edma_set_tcd_to_le(_fsl_chan, _tcd, _val, _field)	\
+#define fsl_edma_set_tcd_to_le_c(_tcd, _val, _field)		\
 do {								\
-	switch (sizeof((_tcd)->_field)) {				\
+	switch (sizeof((_tcd)->_field)) {			\
+	case sizeof(u64):					\
+		(_tcd)->_field = cpu_to_le64(_val);		\
+		break;						\
 	case sizeof(u32):					\
 		(_tcd)->_field = cpu_to_le32(_val);		\
 		break;						\
@@ -269,12 +323,29 @@ do {								\
 	}							\
 } while (0)
 
+#define fsl_edma_set_tcd_to_le(_chan, _tcd, _val, _field)	\
+do {								\
+	if (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64)	\
+		fsl_edma_set_tcd_to_le_c((struct fsl_edma_hw_tcd64 *)_tcd, _val, _field);	\
+	else											\
+		fsl_edma_set_tcd_to_le_c((struct fsl_edma_hw_tcd *)_tcd, _val, _field);		\
+} while (0)
+
 /*
  * R/W functions for big- or little-endian registers:
  * The eDMA controller's endian is independent of the CPU core's endian.
  * For the big-endian IP module, the offset for 8-bit or 16-bit registers
  * should also be swapped opposite to that in little-endian IP.
  */
+static inline u64 edma_readq(struct fsl_edma_engine *edma, void __iomem *addr)
+{
+	/* ioread64 and ioread64be was not defined at some platform */
+	if (edma->big_endian)
+		return swab64(readq(addr));
+	else
+		return readq(addr);
+}
+
 static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
 {
 	if (edma->big_endian)
@@ -320,6 +391,16 @@ static inline void edma_writel(struct fsl_edma_engine *edma,
 		iowrite32(val, addr);
 }
 
+static inline void edma_writeq(struct fsl_edma_engine *edma,
+			       u64 val, void __iomem *addr)
+{
+	/* iowrite64 and iowrite64be was not defined at some platform */
+	if (edma->big_endian)
+		writeq(swab64(val), addr);
+	else
+		writeq(val, addr);
+}
+
 static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
 {
 	return container_of(chan, struct fsl_edma_chan, vchan.chan);
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index 8e5ddeb5e887f..84a5e0666d4f2 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -361,6 +361,16 @@ static struct fsl_edma_drvdata imx93_data4 = {
 	.setup_irq = fsl_edma3_irq_init,
 };
 
+static struct fsl_edma_drvdata imx95_data5 = {
+	.flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4 |
+		 FSL_EDMA_DRV_TCD64,
+	.chreg_space_sz = 0x8000,
+	.chreg_off = 0x10000,
+	.mux_off = 0x200,
+	.mux_skip = sizeof(u32),
+	.setup_irq = fsl_edma3_irq_init,
+};
+
 static const struct of_device_id fsl_edma_dt_ids[] = {
 	{ .compatible = "fsl,vf610-edma", .data = &vf610_data},
 	{ .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
@@ -369,6 +379,7 @@ static const struct of_device_id fsl_edma_dt_ids[] = {
 	{ .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data},
 	{ .compatible = "fsl,imx93-edma3", .data = &imx93_data3},
 	{ .compatible = "fsl,imx93-edma4", .data = &imx93_data4},
+	{ .compatible = "fsl,imx95-edma5", .data = &imx95_data5},
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
@@ -510,6 +521,9 @@ static int fsl_edma_probe(struct platform_device *pdev)
 			return ret;
 	}
 
+	if (drvdata->flags & FSL_EDMA_DRV_TCD64)
+		dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
+
 	INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
 	for (i = 0; i < fsl_edma->n_chans; i++) {
 		struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* Re: [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95
  2023-11-09 21:20 ` [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95 Frank Li
@ 2023-11-10  6:09   ` kernel test robot
  2023-11-10  9:16   ` kernel test robot
                     ` (2 subsequent siblings)
  3 siblings, 0 replies; 15+ messages in thread
From: kernel test robot @ 2023-11-10  6:09 UTC (permalink / raw)
  To: Frank Li
  Cc: oe-kbuild-all, devicetree, dmaengine, imx, joy.zou,
	krzysztof.kozlowski+dt, linux-kernel, peng.fan, robh+dt,
	shenwei.wang, vkoul

Hi Frank,

kernel test robot noticed the following build warnings:

[auto build test WARNING on next-20231109]
[also build test WARNING on linus/master v6.6]
[cannot apply to vkoul-dmaengine/next v6.6 v6.6-rc7 v6.6-rc6]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Frank-Li/dmaengine-fsl-edma-involve-help-macro-fsl_edma_set-get-_tcd/20231110-053023
base:   next-20231109
patch link:    https://lore.kernel.org/r/20231109212059.1894646-5-Frank.Li%40nxp.com
patch subject: [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95
config: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20231110/202311101344.SOhr8axo-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231110/202311101344.SOhr8axo-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202311101344.SOhr8axo-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/dma/mcf-edma-main.c: In function 'mcf_edma_probe':
>> drivers/dma/mcf-edma-main.c:205:46: warning: dereferencing 'void *' pointer
     205 |                 iowrite32(0x0, &mcf_chan->tcd->csr);
         |                                              ^~
   drivers/dma/mcf-edma-main.c:205:46: error: request for member 'csr' in something not a structure or union


vim +205 drivers/dma/mcf-edma-main.c

af802728e4ab07 drivers/dma/mcf-edma.c      Robin Gong         2019-06-25  152  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  153  static int mcf_edma_probe(struct platform_device *pdev)
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  154  {
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  155  	struct mcf_edma_platform_data *pdata;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  156  	struct fsl_edma_engine *mcf_edma;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  157  	struct edma_regs *regs;
923b138388928a drivers/dma/mcf-edma.c      Christophe JAILLET 2023-05-06  158  	int ret, i, chans;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  159  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  160  	pdata = dev_get_platdata(&pdev->dev);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  161  	if (!pdata) {
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  162  		dev_err(&pdev->dev, "no platform data supplied\n");
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  163  		return -EINVAL;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  164  	}
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  165  
0a46781c89dece drivers/dma/mcf-edma.c      Christophe JAILLET 2023-07-12  166  	if (!pdata->dma_channels) {
0a46781c89dece drivers/dma/mcf-edma.c      Christophe JAILLET 2023-07-12  167  		dev_info(&pdev->dev, "setting default channel number to 64");
0a46781c89dece drivers/dma/mcf-edma.c      Christophe JAILLET 2023-07-12  168  		chans = 64;
0a46781c89dece drivers/dma/mcf-edma.c      Christophe JAILLET 2023-07-12  169  	} else {
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  170  		chans = pdata->dma_channels;
0a46781c89dece drivers/dma/mcf-edma.c      Christophe JAILLET 2023-07-12  171  	}
0a46781c89dece drivers/dma/mcf-edma.c      Christophe JAILLET 2023-07-12  172  
923b138388928a drivers/dma/mcf-edma.c      Christophe JAILLET 2023-05-06  173  	mcf_edma = devm_kzalloc(&pdev->dev, struct_size(mcf_edma, chans, chans),
923b138388928a drivers/dma/mcf-edma.c      Christophe JAILLET 2023-05-06  174  				GFP_KERNEL);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  175  	if (!mcf_edma)
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  176  		return -ENOMEM;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  177  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  178  	mcf_edma->n_chans = chans;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  179  
af802728e4ab07 drivers/dma/mcf-edma.c      Robin Gong         2019-06-25  180  	/* Set up drvdata for ColdFire edma */
af802728e4ab07 drivers/dma/mcf-edma.c      Robin Gong         2019-06-25  181  	mcf_edma->drvdata = &mcf_data;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  182  	mcf_edma->big_endian = 1;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  183  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  184  	mutex_init(&mcf_edma->fsl_edma_mutex);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  185  
4b23603a251d24 drivers/dma/mcf-edma.c      Tudor Ambarus      2022-11-10  186  	mcf_edma->membase = devm_platform_ioremap_resource(pdev, 0);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  187  	if (IS_ERR(mcf_edma->membase))
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  188  		return PTR_ERR(mcf_edma->membase);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  189  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  190  	fsl_edma_setup_regs(mcf_edma);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  191  	regs = &mcf_edma->regs;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  192  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  193  	INIT_LIST_HEAD(&mcf_edma->dma_dev.channels);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  194  	for (i = 0; i < mcf_edma->n_chans; i++) {
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  195  		struct fsl_edma_chan *mcf_chan = &mcf_edma->chans[i];
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  196  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  197  		mcf_chan->edma = mcf_edma;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  198  		mcf_chan->slave_id = i;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  199  		mcf_chan->idle = true;
0fa89f972da607 drivers/dma/mcf-edma.c      Laurentiu Tudor    2019-01-18  200  		mcf_chan->dma_dir = DMA_NONE;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  201  		mcf_chan->vchan.desc_free = fsl_edma_free_desc;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  202  		vchan_init(&mcf_chan->vchan, &mcf_edma->dma_dev);
7536f8b371adcc drivers/dma/mcf-edma-main.c Frank Li           2023-08-21  203  		mcf_chan->tcd = mcf_edma->membase + EDMA_TCD
7536f8b371adcc drivers/dma/mcf-edma-main.c Frank Li           2023-08-21  204  				+ i * sizeof(struct fsl_edma_hw_tcd);
7536f8b371adcc drivers/dma/mcf-edma-main.c Frank Li           2023-08-21 @205  		iowrite32(0x0, &mcf_chan->tcd->csr);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  206  	}
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  207  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  208  	iowrite32(~0, regs->inth);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  209  	iowrite32(~0, regs->intl);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  210  
af802728e4ab07 drivers/dma/mcf-edma.c      Robin Gong         2019-06-25  211  	ret = mcf_edma->drvdata->setup_irq(pdev, mcf_edma);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  212  	if (ret)
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  213  		return ret;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  214  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  215  	dma_cap_set(DMA_PRIVATE, mcf_edma->dma_dev.cap_mask);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  216  	dma_cap_set(DMA_SLAVE, mcf_edma->dma_dev.cap_mask);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  217  	dma_cap_set(DMA_CYCLIC, mcf_edma->dma_dev.cap_mask);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  218  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  219  	mcf_edma->dma_dev.dev = &pdev->dev;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  220  	mcf_edma->dma_dev.device_alloc_chan_resources =
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  221  			fsl_edma_alloc_chan_resources;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  222  	mcf_edma->dma_dev.device_free_chan_resources =
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  223  			fsl_edma_free_chan_resources;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  224  	mcf_edma->dma_dev.device_config = fsl_edma_slave_config;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  225  	mcf_edma->dma_dev.device_prep_dma_cyclic =
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  226  			fsl_edma_prep_dma_cyclic;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  227  	mcf_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  228  	mcf_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  229  	mcf_edma->dma_dev.device_pause = fsl_edma_pause;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  230  	mcf_edma->dma_dev.device_resume = fsl_edma_resume;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  231  	mcf_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  232  	mcf_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  233  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  234  	mcf_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  235  	mcf_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  236  	mcf_edma->dma_dev.directions =
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  237  			BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  238  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  239  	mcf_edma->dma_dev.filter.fn = mcf_edma_filter_fn;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  240  	mcf_edma->dma_dev.filter.map = pdata->slave_map;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  241  	mcf_edma->dma_dev.filter.mapcnt = pdata->slavecnt;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  242  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  243  	platform_set_drvdata(pdev, mcf_edma);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  244  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  245  	ret = dma_async_device_register(&mcf_edma->dma_dev);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  246  	if (ret) {
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  247  		dev_err(&pdev->dev,
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  248  			"Can't register Freescale eDMA engine. (%d)\n", ret);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  249  		return ret;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  250  	}
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  251  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  252  	/* Enable round robin arbitration */
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  253  	iowrite32(EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  254  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  255  	return 0;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  256  }
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  257  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95
  2023-11-09 21:20 ` [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95 Frank Li
  2023-11-10  6:09   ` kernel test robot
@ 2023-11-10  9:16   ` kernel test robot
  2023-11-10 14:28   ` kernel test robot
  2023-11-10 14:50   ` Krzysztof Kozlowski
  3 siblings, 0 replies; 15+ messages in thread
From: kernel test robot @ 2023-11-10  9:16 UTC (permalink / raw)
  To: Frank Li
  Cc: oe-kbuild-all, devicetree, dmaengine, imx, joy.zou,
	krzysztof.kozlowski+dt, linux-kernel, peng.fan, robh+dt,
	shenwei.wang, vkoul

Hi Frank,

kernel test robot noticed the following build errors:

[auto build test ERROR on next-20231109]
[also build test ERROR on linus/master v6.6]
[cannot apply to vkoul-dmaengine/next v6.6 v6.6-rc7 v6.6-rc6]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Frank-Li/dmaengine-fsl-edma-involve-help-macro-fsl_edma_set-get-_tcd/20231110-053023
base:   next-20231109
patch link:    https://lore.kernel.org/r/20231109212059.1894646-5-Frank.Li%40nxp.com
patch subject: [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95
config: csky-allmodconfig (https://download.01.org/0day-ci/archive/20231110/202311101713.0LTPV63a-lkp@intel.com/config)
compiler: csky-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231110/202311101713.0LTPV63a-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202311101713.0LTPV63a-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from include/linux/swab.h:5,
                    from include/uapi/linux/byteorder/little_endian.h:14,
                    from include/linux/byteorder/little_endian.h:5,
                    from arch/csky/include/uapi/asm/byteorder.h:6,
                    from include/asm-generic/bitops/le.h:6,
                    from arch/csky/include/asm/bitops.h:77,
                    from include/linux/bitops.h:68,
                    from include/linux/log2.h:12,
                    from include/asm-generic/div64.h:55,
                    from ./arch/csky/include/generated/asm/div64.h:1,
                    from include/linux/math.h:6,
                    from include/linux/math64.h:6,
                    from include/linux/time.h:6,
                    from include/linux/stat.h:19,
                    from include/linux/module.h:13,
                    from drivers/dma/fsl-edma-main.c:12:
   drivers/dma/fsl-edma-common.h: In function 'edma_readq':
>> drivers/dma/fsl-edma-common.h:344:31: error: implicit declaration of function 'readq'; did you mean 'readw'? [-Werror=implicit-function-declaration]
     344 |                 return swab64(readq(addr));
         |                               ^~~~~
   include/uapi/linux/swab.h:128:54: note: in definition of macro '__swab64'
     128 | #define __swab64(x) (__u64)__builtin_bswap64((__u64)(x))
         |                                                      ^
   drivers/dma/fsl-edma-common.h:344:24: note: in expansion of macro 'swab64'
     344 |                 return swab64(readq(addr));
         |                        ^~~~~~
   In file included from drivers/dma/fsl-edma-main.c:22:
   drivers/dma/fsl-edma-common.h: In function 'edma_writeq':
>> drivers/dma/fsl-edma-common.h:399:17: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration]
     399 |                 writeq(swab64(val), addr);
         |                 ^~~~~~
         |                 writel
   cc1: some warnings being treated as errors
--
   In file included from include/linux/swab.h:5,
                    from include/uapi/linux/byteorder/little_endian.h:14,
                    from include/linux/byteorder/little_endian.h:5,
                    from arch/csky/include/uapi/asm/byteorder.h:6,
                    from include/asm-generic/bitops/le.h:6,
                    from arch/csky/include/asm/bitops.h:77,
                    from include/linux/bitops.h:68,
                    from include/linux/log2.h:12,
                    from include/asm-generic/div64.h:55,
                    from ./arch/csky/include/generated/asm/div64.h:1,
                    from include/linux/math.h:6,
                    from include/linux/math64.h:6,
                    from include/linux/time.h:6,
                    from include/linux/stat.h:19,
                    from include/linux/module.h:13,
                    from drivers/dma/mcf-edma-main.c:6:
   drivers/dma/fsl-edma-common.h: In function 'edma_readq':
>> drivers/dma/fsl-edma-common.h:344:31: error: implicit declaration of function 'readq'; did you mean 'readw'? [-Werror=implicit-function-declaration]
     344 |                 return swab64(readq(addr));
         |                               ^~~~~
   include/uapi/linux/swab.h:128:54: note: in definition of macro '__swab64'
     128 | #define __swab64(x) (__u64)__builtin_bswap64((__u64)(x))
         |                                                      ^
   drivers/dma/fsl-edma-common.h:344:24: note: in expansion of macro 'swab64'
     344 |                 return swab64(readq(addr));
         |                        ^~~~~~
   In file included from drivers/dma/mcf-edma-main.c:12:
   drivers/dma/fsl-edma-common.h: In function 'edma_writeq':
>> drivers/dma/fsl-edma-common.h:399:17: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration]
     399 |                 writeq(swab64(val), addr);
         |                 ^~~~~~
         |                 writel
   drivers/dma/mcf-edma-main.c: In function 'mcf_edma_probe':
   drivers/dma/mcf-edma-main.c:205:46: warning: dereferencing 'void *' pointer
     205 |                 iowrite32(0x0, &mcf_chan->tcd->csr);
         |                                              ^~
   drivers/dma/mcf-edma-main.c:205:46: error: request for member 'csr' in something not a structure or union
   cc1: some warnings being treated as errors


vim +344 drivers/dma/fsl-edma-common.h

   333	
   334	/*
   335	 * R/W functions for big- or little-endian registers:
   336	 * The eDMA controller's endian is independent of the CPU core's endian.
   337	 * For the big-endian IP module, the offset for 8-bit or 16-bit registers
   338	 * should also be swapped opposite to that in little-endian IP.
   339	 */
   340	static inline u64 edma_readq(struct fsl_edma_engine *edma, void __iomem *addr)
   341	{
   342		/* ioread64 and ioread64be was not defined at some platform */
   343		if (edma->big_endian)
 > 344			return swab64(readq(addr));
   345		else
   346			return readq(addr);
   347	}
   348	
   349	static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
   350	{
   351		if (edma->big_endian)
   352			return ioread32be(addr);
   353		else
   354			return ioread32(addr);
   355	}
   356	
   357	static inline u16 edma_readw(struct fsl_edma_engine *edma, void __iomem *addr)
   358	{
   359		if (edma->big_endian)
   360			return ioread16be(addr);
   361		else
   362			return ioread16(addr);
   363	}
   364	
   365	static inline void edma_writeb(struct fsl_edma_engine *edma,
   366				       u8 val, void __iomem *addr)
   367	{
   368		/* swap the reg offset for these in big-endian mode */
   369		if (edma->big_endian)
   370			iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
   371		else
   372			iowrite8(val, addr);
   373	}
   374	
   375	static inline void edma_writew(struct fsl_edma_engine *edma,
   376				       u16 val, void __iomem *addr)
   377	{
   378		/* swap the reg offset for these in big-endian mode */
   379		if (edma->big_endian)
   380			iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
   381		else
   382			iowrite16(val, addr);
   383	}
   384	
   385	static inline void edma_writel(struct fsl_edma_engine *edma,
   386				       u32 val, void __iomem *addr)
   387	{
   388		if (edma->big_endian)
   389			iowrite32be(val, addr);
   390		else
   391			iowrite32(val, addr);
   392	}
   393	
   394	static inline void edma_writeq(struct fsl_edma_engine *edma,
   395				       u64 val, void __iomem *addr)
   396	{
   397		/* iowrite64 and iowrite64be was not defined at some platform */
   398		if (edma->big_endian)
 > 399			writeq(swab64(val), addr);
   400		else
   401			writeq(val, addr);
   402	}
   403	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95
  2023-11-09 21:20 ` [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95 Frank Li
  2023-11-10  6:09   ` kernel test robot
  2023-11-10  9:16   ` kernel test robot
@ 2023-11-10 14:28   ` kernel test robot
  2023-11-10 14:50   ` Krzysztof Kozlowski
  3 siblings, 0 replies; 15+ messages in thread
From: kernel test robot @ 2023-11-10 14:28 UTC (permalink / raw)
  To: Frank Li
  Cc: oe-kbuild-all, devicetree, dmaengine, imx, joy.zou,
	krzysztof.kozlowski+dt, linux-kernel, peng.fan, robh+dt,
	shenwei.wang, vkoul

Hi Frank,

kernel test robot noticed the following build errors:

[auto build test ERROR on next-20231109]
[also build test ERROR on linus/master v6.6]
[cannot apply to vkoul-dmaengine/next v6.6 v6.6-rc7 v6.6-rc6]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Frank-Li/dmaengine-fsl-edma-involve-help-macro-fsl_edma_set-get-_tcd/20231110-053023
base:   next-20231109
patch link:    https://lore.kernel.org/r/20231109212059.1894646-5-Frank.Li%40nxp.com
patch subject: [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95
config: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20231110/202311102230.c9Xl4AcZ-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231110/202311102230.c9Xl4AcZ-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202311102230.c9Xl4AcZ-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/dma/mcf-edma-main.c: In function 'mcf_edma_probe':
   drivers/dma/mcf-edma-main.c:205:46: warning: dereferencing 'void *' pointer
     205 |                 iowrite32(0x0, &mcf_chan->tcd->csr);
         |                                              ^~
>> drivers/dma/mcf-edma-main.c:205:46: error: request for member 'csr' in something not a structure or union


vim +/csr +205 drivers/dma/mcf-edma-main.c

af802728e4ab07 drivers/dma/mcf-edma.c      Robin Gong         2019-06-25  152  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  153  static int mcf_edma_probe(struct platform_device *pdev)
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  154  {
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  155  	struct mcf_edma_platform_data *pdata;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  156  	struct fsl_edma_engine *mcf_edma;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  157  	struct edma_regs *regs;
923b138388928a drivers/dma/mcf-edma.c      Christophe JAILLET 2023-05-06  158  	int ret, i, chans;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  159  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  160  	pdata = dev_get_platdata(&pdev->dev);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  161  	if (!pdata) {
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  162  		dev_err(&pdev->dev, "no platform data supplied\n");
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  163  		return -EINVAL;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  164  	}
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  165  
0a46781c89dece drivers/dma/mcf-edma.c      Christophe JAILLET 2023-07-12  166  	if (!pdata->dma_channels) {
0a46781c89dece drivers/dma/mcf-edma.c      Christophe JAILLET 2023-07-12  167  		dev_info(&pdev->dev, "setting default channel number to 64");
0a46781c89dece drivers/dma/mcf-edma.c      Christophe JAILLET 2023-07-12  168  		chans = 64;
0a46781c89dece drivers/dma/mcf-edma.c      Christophe JAILLET 2023-07-12  169  	} else {
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  170  		chans = pdata->dma_channels;
0a46781c89dece drivers/dma/mcf-edma.c      Christophe JAILLET 2023-07-12  171  	}
0a46781c89dece drivers/dma/mcf-edma.c      Christophe JAILLET 2023-07-12  172  
923b138388928a drivers/dma/mcf-edma.c      Christophe JAILLET 2023-05-06  173  	mcf_edma = devm_kzalloc(&pdev->dev, struct_size(mcf_edma, chans, chans),
923b138388928a drivers/dma/mcf-edma.c      Christophe JAILLET 2023-05-06  174  				GFP_KERNEL);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  175  	if (!mcf_edma)
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  176  		return -ENOMEM;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  177  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  178  	mcf_edma->n_chans = chans;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  179  
af802728e4ab07 drivers/dma/mcf-edma.c      Robin Gong         2019-06-25  180  	/* Set up drvdata for ColdFire edma */
af802728e4ab07 drivers/dma/mcf-edma.c      Robin Gong         2019-06-25  181  	mcf_edma->drvdata = &mcf_data;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  182  	mcf_edma->big_endian = 1;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  183  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  184  	mutex_init(&mcf_edma->fsl_edma_mutex);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  185  
4b23603a251d24 drivers/dma/mcf-edma.c      Tudor Ambarus      2022-11-10  186  	mcf_edma->membase = devm_platform_ioremap_resource(pdev, 0);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  187  	if (IS_ERR(mcf_edma->membase))
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  188  		return PTR_ERR(mcf_edma->membase);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  189  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  190  	fsl_edma_setup_regs(mcf_edma);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  191  	regs = &mcf_edma->regs;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  192  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  193  	INIT_LIST_HEAD(&mcf_edma->dma_dev.channels);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  194  	for (i = 0; i < mcf_edma->n_chans; i++) {
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  195  		struct fsl_edma_chan *mcf_chan = &mcf_edma->chans[i];
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  196  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  197  		mcf_chan->edma = mcf_edma;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  198  		mcf_chan->slave_id = i;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  199  		mcf_chan->idle = true;
0fa89f972da607 drivers/dma/mcf-edma.c      Laurentiu Tudor    2019-01-18  200  		mcf_chan->dma_dir = DMA_NONE;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  201  		mcf_chan->vchan.desc_free = fsl_edma_free_desc;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  202  		vchan_init(&mcf_chan->vchan, &mcf_edma->dma_dev);
7536f8b371adcc drivers/dma/mcf-edma-main.c Frank Li           2023-08-21  203  		mcf_chan->tcd = mcf_edma->membase + EDMA_TCD
7536f8b371adcc drivers/dma/mcf-edma-main.c Frank Li           2023-08-21  204  				+ i * sizeof(struct fsl_edma_hw_tcd);
7536f8b371adcc drivers/dma/mcf-edma-main.c Frank Li           2023-08-21 @205  		iowrite32(0x0, &mcf_chan->tcd->csr);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  206  	}
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  207  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  208  	iowrite32(~0, regs->inth);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  209  	iowrite32(~0, regs->intl);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  210  
af802728e4ab07 drivers/dma/mcf-edma.c      Robin Gong         2019-06-25  211  	ret = mcf_edma->drvdata->setup_irq(pdev, mcf_edma);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  212  	if (ret)
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  213  		return ret;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  214  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  215  	dma_cap_set(DMA_PRIVATE, mcf_edma->dma_dev.cap_mask);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  216  	dma_cap_set(DMA_SLAVE, mcf_edma->dma_dev.cap_mask);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  217  	dma_cap_set(DMA_CYCLIC, mcf_edma->dma_dev.cap_mask);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  218  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  219  	mcf_edma->dma_dev.dev = &pdev->dev;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  220  	mcf_edma->dma_dev.device_alloc_chan_resources =
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  221  			fsl_edma_alloc_chan_resources;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  222  	mcf_edma->dma_dev.device_free_chan_resources =
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  223  			fsl_edma_free_chan_resources;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  224  	mcf_edma->dma_dev.device_config = fsl_edma_slave_config;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  225  	mcf_edma->dma_dev.device_prep_dma_cyclic =
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  226  			fsl_edma_prep_dma_cyclic;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  227  	mcf_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  228  	mcf_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  229  	mcf_edma->dma_dev.device_pause = fsl_edma_pause;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  230  	mcf_edma->dma_dev.device_resume = fsl_edma_resume;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  231  	mcf_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  232  	mcf_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  233  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  234  	mcf_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  235  	mcf_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  236  	mcf_edma->dma_dev.directions =
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  237  			BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  238  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  239  	mcf_edma->dma_dev.filter.fn = mcf_edma_filter_fn;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  240  	mcf_edma->dma_dev.filter.map = pdata->slave_map;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  241  	mcf_edma->dma_dev.filter.mapcnt = pdata->slavecnt;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  242  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  243  	platform_set_drvdata(pdev, mcf_edma);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  244  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  245  	ret = dma_async_device_register(&mcf_edma->dma_dev);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  246  	if (ret) {
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  247  		dev_err(&pdev->dev,
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  248  			"Can't register Freescale eDMA engine. (%d)\n", ret);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  249  		return ret;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  250  	}
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  251  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  252  	/* Enable round robin arbitration */
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  253  	iowrite32(EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  254  
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  255  	return 0;
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  256  }
e7a3ff92eaf19e drivers/dma/mcf-edma.c      Angelo Dureghello  2018-08-19  257  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95
  2023-11-09 21:20 ` [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95 Frank Li
                     ` (2 preceding siblings ...)
  2023-11-10 14:28   ` kernel test robot
@ 2023-11-10 14:50   ` Krzysztof Kozlowski
  2023-11-10 14:59     ` Frank Li
  3 siblings, 1 reply; 15+ messages in thread
From: Krzysztof Kozlowski @ 2023-11-10 14:50 UTC (permalink / raw)
  To: Frank Li
  Cc: devicetree, dmaengine, imx, joy.zou, krzysztof.kozlowski+dt,
	linux-kernel, peng.fan, robh+dt, shenwei.wang, vkoul

On 09/11/2023 22:20, Frank Li wrote:
> In i.MX95's edma version 5, the TCD structure is extended to support 64-bit
> addresses for fields like saddr and daddr. To prevent code duplication,
> employ help macros to handle the fields, as the field names remain the same
> between TCD and TCD64.
> 
> Change local variables related to TCD addresses from 'u32' to 'dma_addr_t'
> to accept 64-bit DMA addresses.
> 
> Change 'vtcd' type to 'void *' to avoid direct use. Use helper macros to
> access the TCD fields correctly.
> 
> Call 'dma_set_mask_and_coherent(64)' when TCD64 is supported.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---

Three kbuild reports with build failures.

I have impression this was never build-tested and reviewed internally
before posting. We had such talk ~month ago and I insisted on some
internal review prior submitting to mailing list. I did not insist on
internal building of patches, because it felt obvious, so please kindly
thoroughly build, review and test your patches internally, before using
the community for this. I am pretty sure NXP can build the code they send.

Thank you in advance.

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95
  2023-11-10 14:50   ` Krzysztof Kozlowski
@ 2023-11-10 14:59     ` Frank Li
  2023-11-10 15:10       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 15+ messages in thread
From: Frank Li @ 2023-11-10 14:59 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: devicetree, dmaengine, imx, joy.zou, krzysztof.kozlowski+dt,
	linux-kernel, peng.fan, robh+dt, shenwei.wang, vkoul

On Fri, Nov 10, 2023 at 03:50:18PM +0100, Krzysztof Kozlowski wrote:
> On 09/11/2023 22:20, Frank Li wrote:
> > In i.MX95's edma version 5, the TCD structure is extended to support 64-bit
> > addresses for fields like saddr and daddr. To prevent code duplication,
> > employ help macros to handle the fields, as the field names remain the same
> > between TCD and TCD64.
> > 
> > Change local variables related to TCD addresses from 'u32' to 'dma_addr_t'
> > to accept 64-bit DMA addresses.
> > 
> > Change 'vtcd' type to 'void *' to avoid direct use. Use helper macros to
> > access the TCD fields correctly.
> > 
> > Call 'dma_set_mask_and_coherent(64)' when TCD64 is supported.
> > 
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> 
> Three kbuild reports with build failures.
> 
> I have impression this was never build-tested and reviewed internally
> before posting. We had such talk ~month ago and I insisted on some
> internal review prior submitting to mailing list. I did not insist on
> internal building of patches, because it felt obvious, so please kindly
> thoroughly build, review and test your patches internally, before using
> the community for this. I am pretty sure NXP can build the code they send.

This build error happen at on special uncommon platform m6800. 
Patch is tested in imx95 arm64 platform.

I have not machine to cover all platform.

Frank

> 
> Thank you in advance.
> 
> Best regards,
> Krzysztof
> 

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95
  2023-11-10 14:59     ` Frank Li
@ 2023-11-10 15:10       ` Krzysztof Kozlowski
  2023-11-10 15:36         ` Frank Li
  0 siblings, 1 reply; 15+ messages in thread
From: Krzysztof Kozlowski @ 2023-11-10 15:10 UTC (permalink / raw)
  To: Frank Li
  Cc: devicetree, dmaengine, imx, joy.zou, krzysztof.kozlowski+dt,
	linux-kernel, peng.fan, robh+dt, shenwei.wang, vkoul

On 10/11/2023 15:59, Frank Li wrote:
>>>
>>> Signed-off-by: Frank Li <Frank.Li@nxp.com>
>>> ---
>>
>> Three kbuild reports with build failures.
>>
>> I have impression this was never build-tested and reviewed internally
>> before posting. We had such talk ~month ago and I insisted on some
>> internal review prior submitting to mailing list. I did not insist on
>> internal building of patches, because it felt obvious, so please kindly
>> thoroughly build, review and test your patches internally, before using
>> the community for this. I am pretty sure NXP can build the code they send.
> 
> This build error happen at on special uncommon platform m6800. 

Indeed csky and alpha are special. Let's see if LKP will find other
platforms as well.

> Patch is tested in imx95 arm64 platform.

That's not enough. It's trivial to build test on riscv, ppc, x86_64 and
i386. Building on only one platform is not that much.

> 
> I have not machine to cover all platform.

I was able to do it as a hobbyist, on my poor laptop. What is exactly
the problem that as hobbyist I can, but NXP cannot?

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95
  2023-11-10 15:10       ` Krzysztof Kozlowski
@ 2023-11-10 15:36         ` Frank Li
  2023-11-10 15:52           ` Krzysztof Kozlowski
  0 siblings, 1 reply; 15+ messages in thread
From: Frank Li @ 2023-11-10 15:36 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: devicetree, dmaengine, imx, joy.zou, krzysztof.kozlowski+dt,
	linux-kernel, peng.fan, robh+dt, shenwei.wang, vkoul

On Fri, Nov 10, 2023 at 04:10:46PM +0100, Krzysztof Kozlowski wrote:
> On 10/11/2023 15:59, Frank Li wrote:
> >>>
> >>> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> >>> ---
> >>
> >> Three kbuild reports with build failures.
> >>
> >> I have impression this was never build-tested and reviewed internally
> >> before posting. We had such talk ~month ago and I insisted on some
> >> internal review prior submitting to mailing list. I did not insist on
> >> internal building of patches, because it felt obvious, so please kindly
> >> thoroughly build, review and test your patches internally, before using
> >> the community for this. I am pretty sure NXP can build the code they send.
> > 
> > This build error happen at on special uncommon platform m6800. 
> 
> Indeed csky and alpha are special. Let's see if LKP will find other
> platforms as well.
> 
> > Patch is tested in imx95 arm64 platform.
> 
> That's not enough. It's trivial to build test on riscv, ppc, x86_64 and
> i386. Building on only one platform is not that much.
> 
> > 
> > I have not machine to cover all platform.
> 
> I was able to do it as a hobbyist, on my poor laptop. What is exactly
> the problem that as hobbyist I can, but NXP cannot?

There are also difference configs. I think 'kernel test robot' is very good
tools. If there are guide to mirror it, we can try. It is not neccesary to
duplicate to develop a build test infrastrue.

The issue is not that run build test. The key problem is how to know a
protential problem will be exist, and limited a build/config scrope.

Even I have risc\ppc\x86_64 built before I submmit patch, still can't
capture build error if I missed just one platform mc6800.

For `readq` error also depend on the configs.

Actually, we major focus on test edmav1, .... v5 at difference platforms
before submit patches. 

> 
> Best regards,
> Krzysztof
> 

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95
  2023-11-10 15:36         ` Frank Li
@ 2023-11-10 15:52           ` Krzysztof Kozlowski
  2023-11-10 16:08             ` Frank Li
  0 siblings, 1 reply; 15+ messages in thread
From: Krzysztof Kozlowski @ 2023-11-10 15:52 UTC (permalink / raw)
  To: Frank Li
  Cc: devicetree, dmaengine, imx, joy.zou, krzysztof.kozlowski+dt,
	linux-kernel, peng.fan, robh+dt, shenwei.wang, vkoul

On 10/11/2023 16:36, Frank Li wrote:
> On Fri, Nov 10, 2023 at 04:10:46PM +0100, Krzysztof Kozlowski wrote:
>> On 10/11/2023 15:59, Frank Li wrote:
>>>>>
>>>>> Signed-off-by: Frank Li <Frank.Li@nxp.com>
>>>>> ---
>>>>
>>>> Three kbuild reports with build failures.
>>>>
>>>> I have impression this was never build-tested and reviewed internally
>>>> before posting. We had such talk ~month ago and I insisted on some
>>>> internal review prior submitting to mailing list. I did not insist on
>>>> internal building of patches, because it felt obvious, so please kindly
>>>> thoroughly build, review and test your patches internally, before using
>>>> the community for this. I am pretty sure NXP can build the code they send.
>>>
>>> This build error happen at on special uncommon platform m6800. 
>>
>> Indeed csky and alpha are special. Let's see if LKP will find other
>> platforms as well.
>>
>>> Patch is tested in imx95 arm64 platform.
>>
>> That's not enough. It's trivial to build test on riscv, ppc, x86_64 and
>> i386. Building on only one platform is not that much.
>>
>>>
>>> I have not machine to cover all platform.
>>
>> I was able to do it as a hobbyist, on my poor laptop. What is exactly
>> the problem that as hobbyist I can, but NXP cannot?
> 
> There are also difference configs. I think 'kernel test robot' is very good
> tools. If there are guide to mirror it, we can try. It is not neccesary to
> duplicate to develop a build test infrastrue.

Sorry, there is no build infrastructure here. I done it on my laptop.

> 
> The issue is not that run build test. The key problem is how to know a
> protential problem will be exist, and limited a build/config scrope.

These are all the trivial configs - allyes and allmod.

> 
> Even I have risc\ppc\x86_64 built before I submmit patch, still can't
> capture build error if I missed just one platform mc6800.

So you did not read these build reports. This is not "mc6800" platform.
This is allyes and allmod, the most obvious builds, after defconfig.

> 
> For `readq` error also depend on the configs.

Read again the build reports from LKP.

> 
> Actually, we major focus on test edmav1, .... v5 at difference platforms
> before submit patches. 


Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95
  2023-11-10 15:52           ` Krzysztof Kozlowski
@ 2023-11-10 16:08             ` Frank Li
  0 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2023-11-10 16:08 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: devicetree, dmaengine, imx, joy.zou, krzysztof.kozlowski+dt,
	linux-kernel, peng.fan, robh+dt, shenwei.wang, vkoul

On Fri, Nov 10, 2023 at 04:52:49PM +0100, Krzysztof Kozlowski wrote:
> On 10/11/2023 16:36, Frank Li wrote:
> > On Fri, Nov 10, 2023 at 04:10:46PM +0100, Krzysztof Kozlowski wrote:
> >> On 10/11/2023 15:59, Frank Li wrote:
> >>>>>
> >>>>> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> >>>>> ---
> >>>>
> >>>> Three kbuild reports with build failures.
> >>>>
> >>>> I have impression this was never build-tested and reviewed internally
> >>>> before posting. We had such talk ~month ago and I insisted on some
> >>>> internal review prior submitting to mailing list. I did not insist on
> >>>> internal building of patches, because it felt obvious, so please kindly
> >>>> thoroughly build, review and test your patches internally, before using
> >>>> the community for this. I am pretty sure NXP can build the code they send.
> >>>
> >>> This build error happen at on special uncommon platform m6800. 
> >>
> >> Indeed csky and alpha are special. Let's see if LKP will find other
> >> platforms as well.
> >>
> >>> Patch is tested in imx95 arm64 platform.
> >>
> >> That's not enough. It's trivial to build test on riscv, ppc, x86_64 and
> >> i386. Building on only one platform is not that much.
> >>
> >>>
> >>> I have not machine to cover all platform.
> >>
> >> I was able to do it as a hobbyist, on my poor laptop. What is exactly
> >> the problem that as hobbyist I can, but NXP cannot?
> > 
> > There are also difference configs. I think 'kernel test robot' is very good
> > tools. If there are guide to mirror it, we can try. It is not neccesary to
> > duplicate to develop a build test infrastrue.
> 
> Sorry, there is no build infrastructure here. I done it on my laptop.
> 
> > 
> > The issue is not that run build test. The key problem is how to know a
> > protential problem will be exist, and limited a build/config scrope.
> 
> These are all the trivial configs - allyes and allmod.

Thanks let me know about allyes and allmod.

> 
> > 
> > Even I have risc\ppc\x86_64 built before I submmit patch, still can't
> > capture build error if I missed just one platform mc6800.
> 
> So you did not read these build reports. This is not "mc6800" platform.
> This is allyes and allmod, the most obvious builds, after defconfig.

Sorry, I have not read it carefully. Just glance happen at mcf_xxx. I known
I missed test this platform.

Generally, I read carefully when I work on the fix patches.

> 
> > 
> > For `readq` error also depend on the configs.
> 
> Read again the build reports from LKP.
> 
> > 
> > Actually, we major focus on test edmav1, .... v5 at difference platforms
> > before submit patches. 
> 
> 
> Best regards,
> Krzysztof
> 

^ permalink raw reply	[flat|nested] 15+ messages in thread

end of thread, other threads:[~2023-11-10 16:08 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-11-09 21:20 [PATCH 0/4] dmaengine: fsl-edma: integrate TCD64 support for 64bit physical address Frank Li
2023-11-09 21:20 ` [PATCH 1/4] dmaengine: fsl-edma: involve help macro fsl_edma_set(get)_tcd() Frank Li
2023-11-09 21:20 ` [PATCH 2/4] dmaengine: fsl-edma: add address for channel mux register in fsl_edma_chan Frank Li
2023-11-09 21:20 ` [PATCH 3/4] dt-bindings: fsl-dma: fsl-edma: add fsl,imx95-edma5 compatible string Frank Li
2023-11-10  7:56   ` Krzysztof Kozlowski
2023-11-09 21:20 ` [PATCH 4/4] dmaengine: fsl-edma: integrate TCD64 support for i.MX95 Frank Li
2023-11-10  6:09   ` kernel test robot
2023-11-10  9:16   ` kernel test robot
2023-11-10 14:28   ` kernel test robot
2023-11-10 14:50   ` Krzysztof Kozlowski
2023-11-10 14:59     ` Frank Li
2023-11-10 15:10       ` Krzysztof Kozlowski
2023-11-10 15:36         ` Frank Li
2023-11-10 15:52           ` Krzysztof Kozlowski
2023-11-10 16:08             ` Frank Li

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