* [PATCH v2 2/4] clk: rs9: Limit check to vendor ID in VID register
2023-11-11 16:06 [PATCH v2 1/4] dt-bindings: clk: rs9: Add 9FGV0841 Marek Vasut
@ 2023-11-11 16:07 ` Marek Vasut
2023-11-11 16:51 ` Biju Das
2023-11-11 16:07 ` [PATCH v2 3/4] clk: rs9: Replace model check with bitshift from chip data Marek Vasut
2023-11-11 16:07 ` [PATCH v2 4/4] clk: rs9: Add support for 9FGV0841 Marek Vasut
2 siblings, 1 reply; 8+ messages in thread
From: Marek Vasut @ 2023-11-11 16:07 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Alexander Stein, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Michael Turquette, Rob Herring, Stephen Boyd,
devicetree, linux-renesas-soc
Extract only vendor ID from VID register, the top 4 bits are
revision ID which are not useful for the vendor ID check.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Alexander Stein <alexander.stein@ew.tq-group.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
V2: Split off patch from 4/4
---
drivers/clk/clk-renesas-pcie.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c
index 6606aba253c5..b5c430e4899c 100644
--- a/drivers/clk/clk-renesas-pcie.c
+++ b/drivers/clk/clk-renesas-pcie.c
@@ -42,6 +42,7 @@
#define RS9_REG_DID 0x6
#define RS9_REG_BCP 0x7
+#define RS9_REG_VID_MASK GENMASK(3, 0)
#define RS9_REG_VID_IDT 0x01
#define RS9_REG_DID_TYPE_FGV (0x0 << RS9_REG_DID_TYPE_SHIFT)
@@ -333,6 +334,7 @@ static int rs9_probe(struct i2c_client *client)
if (ret < 0)
return ret;
+ vid &= RS9_REG_VID_MASK;
if (vid != RS9_REG_VID_IDT || did != rs9->chip_info->did)
return dev_err_probe(&client->dev, -ENODEV,
"Incorrect VID/DID: %#02x, %#02x. Expected %#02x, %#02x\n",
--
2.42.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* RE: [PATCH v2 2/4] clk: rs9: Limit check to vendor ID in VID register
2023-11-11 16:07 ` [PATCH v2 2/4] clk: rs9: Limit check to vendor ID in VID register Marek Vasut
@ 2023-11-11 16:51 ` Biju Das
0 siblings, 0 replies; 8+ messages in thread
From: Biju Das @ 2023-11-11 16:51 UTC (permalink / raw)
To: Marek Vasut, linux-clk@vger.kernel.org
Cc: Alexander Stein, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Michael Turquette, Rob Herring, Stephen Boyd,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Hi Marek Vasut,
Thanks for the patch.
> Subject: [PATCH v2 2/4] clk: rs9: Limit check to vendor ID in VID register
>
> Extract only vendor ID from VID register, the top 4 bits are revision ID
> which are not useful for the vendor ID check.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Cheers,
Biju
> ---
> Cc: Alexander Stein <alexander.stein@ew.tq-group.com>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-renesas-soc@vger.kernel.org
> ---
> V2: Split off patch from 4/4
> ---
> drivers/clk/clk-renesas-pcie.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-
> pcie.c index 6606aba253c5..b5c430e4899c 100644
> --- a/drivers/clk/clk-renesas-pcie.c
> +++ b/drivers/clk/clk-renesas-pcie.c
> @@ -42,6 +42,7 @@
> #define RS9_REG_DID 0x6
> #define RS9_REG_BCP 0x7
>
> +#define RS9_REG_VID_MASK GENMASK(3, 0)
> #define RS9_REG_VID_IDT 0x01
>
> #define RS9_REG_DID_TYPE_FGV (0x0 << RS9_REG_DID_TYPE_SHIFT)
> @@ -333,6 +334,7 @@ static int rs9_probe(struct i2c_client *client)
> if (ret < 0)
> return ret;
>
> + vid &= RS9_REG_VID_MASK;
> if (vid != RS9_REG_VID_IDT || did != rs9->chip_info->did)
> return dev_err_probe(&client->dev, -ENODEV,
> "Incorrect VID/DID: %#02x, %#02x.
> Expected %#02x, %#02x\n",
> --
> 2.42.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/4] clk: rs9: Replace model check with bitshift from chip data
2023-11-11 16:06 [PATCH v2 1/4] dt-bindings: clk: rs9: Add 9FGV0841 Marek Vasut
2023-11-11 16:07 ` [PATCH v2 2/4] clk: rs9: Limit check to vendor ID in VID register Marek Vasut
@ 2023-11-11 16:07 ` Marek Vasut
2023-11-11 16:14 ` Biju Das
2023-11-11 16:07 ` [PATCH v2 4/4] clk: rs9: Add support for 9FGV0841 Marek Vasut
2 siblings, 1 reply; 8+ messages in thread
From: Marek Vasut @ 2023-11-11 16:07 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Alexander Stein, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Michael Turquette, Rob Herring, Stephen Boyd,
devicetree, linux-renesas-soc
Adjust rs9_calc_dif() to special-case the 9FGV0241 where DIFx bits
start at 1, encode this shift into chip data and drop the model
check entirely.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Alexander Stein <alexander.stein@ew.tq-group.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
V2: New patch
---
drivers/clk/clk-renesas-pcie.c | 20 +++++++++-----------
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c
index b5c430e4899c..5064016afbc3 100644
--- a/drivers/clk/clk-renesas-pcie.c
+++ b/drivers/clk/clk-renesas-pcie.c
@@ -58,8 +58,8 @@ enum rs9_model {
/* Structure to describe features of a particular 9-series model */
struct rs9_chip_info {
- const enum rs9_model model;
unsigned int num_clks;
+ u8 outshift;
u8 did;
};
@@ -161,14 +161,12 @@ static const struct regmap_config rs9_regmap_config = {
static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx)
{
- enum rs9_model model = rs9->chip_info->model;
-
- if (model == RENESAS_9FGV0241)
- return BIT(idx + 1);
- else if (model == RENESAS_9FGV0441)
- return BIT(idx);
-
- return 0;
+ /*
+ * On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE(1) is BIT(2),
+ * on 9FGV0441 and 9FGV0841 the DIF OE0 is BIT(0) and so on.
+ * Increment the index in the 9FGV0241 special case here.
+ */
+ return BIT(idx + rs9->chip_info->outshift);
}
static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx)
@@ -382,14 +380,14 @@ static int __maybe_unused rs9_resume(struct device *dev)
}
static const struct rs9_chip_info renesas_9fgv0241_info = {
- .model = RENESAS_9FGV0241,
.num_clks = 2,
+ .outshift = 1,
.did = RS9_REG_DID_TYPE_FGV | 0x02,
};
static const struct rs9_chip_info renesas_9fgv0441_info = {
- .model = RENESAS_9FGV0441,
.num_clks = 4,
+ .outshift = 0,
.did = RS9_REG_DID_TYPE_FGV | 0x04,
};
--
2.42.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* RE: [PATCH v2 3/4] clk: rs9: Replace model check with bitshift from chip data
2023-11-11 16:07 ` [PATCH v2 3/4] clk: rs9: Replace model check with bitshift from chip data Marek Vasut
@ 2023-11-11 16:14 ` Biju Das
2023-11-11 16:18 ` Marek Vasut
0 siblings, 1 reply; 8+ messages in thread
From: Biju Das @ 2023-11-11 16:14 UTC (permalink / raw)
To: Marek Vasut, linux-clk@vger.kernel.org
Cc: Alexander Stein, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Michael Turquette, Rob Herring, Stephen Boyd,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Hi Marek Vasut,
> Subject: [PATCH v2 3/4] clk: rs9: Replace model check with bitshift from
> chip data
>
> Adjust rs9_calc_dif() to special-case the 9FGV0241 where DIFx bits start
> at 1, encode this shift into chip data and drop the model check entirely.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> ---
> Cc: Alexander Stein <alexander.stein@ew.tq-group.com>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-renesas-soc@vger.kernel.org
> ---
> V2: New patch
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Do you need enum rs9_model as it is unused after this patch??
Cheers,
Biju
> ---
> drivers/clk/clk-renesas-pcie.c | 20 +++++++++-----------
> 1 file changed, 9 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-
> pcie.c index b5c430e4899c..5064016afbc3 100644
> --- a/drivers/clk/clk-renesas-pcie.c
> +++ b/drivers/clk/clk-renesas-pcie.c
> @@ -58,8 +58,8 @@ enum rs9_model {
>
> /* Structure to describe features of a particular 9-series model */
> struct rs9_chip_info {
> - const enum rs9_model model;
> unsigned int num_clks;
> + u8 outshift;
> u8 did;
> };
>
> @@ -161,14 +161,12 @@ static const struct regmap_config rs9_regmap_config
> = {
>
> static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx) {
> - enum rs9_model model = rs9->chip_info->model;
> -
> - if (model == RENESAS_9FGV0241)
> - return BIT(idx + 1);
> - else if (model == RENESAS_9FGV0441)
> - return BIT(idx);
> -
> - return 0;
> + /*
> + * On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE(1) is BIT(2),
> + * on 9FGV0441 and 9FGV0841 the DIF OE0 is BIT(0) and so on.
> + * Increment the index in the 9FGV0241 special case here.
> + */
> + return BIT(idx + rs9->chip_info->outshift);
> }
>
> static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx) @@
> -382,14 +380,14 @@ static int __maybe_unused rs9_resume(struct device
> *dev) }
>
> static const struct rs9_chip_info renesas_9fgv0241_info = {
> - .model = RENESAS_9FGV0241,
> .num_clks = 2,
> + .outshift = 1,
> .did = RS9_REG_DID_TYPE_FGV | 0x02,
> };
>
> static const struct rs9_chip_info renesas_9fgv0441_info = {
> - .model = RENESAS_9FGV0441,
> .num_clks = 4,
> + .outshift = 0,
> .did = RS9_REG_DID_TYPE_FGV | 0x04,
> };
>
> --
> 2.42.0
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v2 3/4] clk: rs9: Replace model check with bitshift from chip data
2023-11-11 16:14 ` Biju Das
@ 2023-11-11 16:18 ` Marek Vasut
0 siblings, 0 replies; 8+ messages in thread
From: Marek Vasut @ 2023-11-11 16:18 UTC (permalink / raw)
To: Biju Das, Marek Vasut, linux-clk@vger.kernel.org
Cc: Alexander Stein, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Michael Turquette, Rob Herring, Stephen Boyd,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
On 11/11/23 17:14, Biju Das wrote:
> Hi Marek Vasut,
>
>> Subject: [PATCH v2 3/4] clk: rs9: Replace model check with bitshift from
>> chip data
>>
>> Adjust rs9_calc_dif() to special-case the 9FGV0241 where DIFx bits start
>> at 1, encode this shift into chip data and drop the model check entirely.
>>
>> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
>> ---
>> Cc: Alexander Stein <alexander.stein@ew.tq-group.com>
>> Cc: Conor Dooley <conor+dt@kernel.org>
>> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
>> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
>> Cc: Michael Turquette <mturquette@baylibre.com>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Stephen Boyd <sboyd@kernel.org>
>> Cc: devicetree@vger.kernel.org
>> Cc: linux-clk@vger.kernel.org
>> Cc: linux-renesas-soc@vger.kernel.org
>> ---
>> V2: New patch
>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
>
> Do you need enum rs9_model as it is unused after this patch??
Dropped in V3 , thanks.
Can you check the other patches too ? I'll send V3 tomorrow-ish.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 4/4] clk: rs9: Add support for 9FGV0841
2023-11-11 16:06 [PATCH v2 1/4] dt-bindings: clk: rs9: Add 9FGV0841 Marek Vasut
2023-11-11 16:07 ` [PATCH v2 2/4] clk: rs9: Limit check to vendor ID in VID register Marek Vasut
2023-11-11 16:07 ` [PATCH v2 3/4] clk: rs9: Replace model check with bitshift from chip data Marek Vasut
@ 2023-11-11 16:07 ` Marek Vasut
2023-11-11 16:49 ` Biju Das
2 siblings, 1 reply; 8+ messages in thread
From: Marek Vasut @ 2023-11-11 16:07 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Alexander Stein, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Michael Turquette, Rob Herring, Stephen Boyd,
devicetree, linux-renesas-soc
This model is similar to 9FGV0441, the DIFx bits start at bit 0 again,
except this chip has 8 outputs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Alexander Stein <alexander.stein@ew.tq-group.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
V2: Update on top of 2/4 and 3/4
---
drivers/clk/clk-renesas-pcie.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c
index 5064016afbc3..6d494e5f8fa7 100644
--- a/drivers/clk/clk-renesas-pcie.c
+++ b/drivers/clk/clk-renesas-pcie.c
@@ -7,6 +7,7 @@
* Currently supported:
* - 9FGV0241
* - 9FGV0441
+ * - 9FGV0841
*
* Copyright (C) 2022 Marek Vasut <marex@denx.de>
*/
@@ -54,6 +55,7 @@
enum rs9_model {
RENESAS_9FGV0241,
RENESAS_9FGV0441,
+ RENESAS_9FGV0841,
};
/* Structure to describe features of a particular 9-series model */
@@ -391,9 +393,16 @@ static const struct rs9_chip_info renesas_9fgv0441_info = {
.did = RS9_REG_DID_TYPE_FGV | 0x04,
};
+static const struct rs9_chip_info renesas_9fgv0841_info = {
+ .num_clks = 8,
+ .outshift = 0,
+ .did = RS9_REG_DID_TYPE_FGV | 0x08,
+};
+
static const struct i2c_device_id rs9_id[] = {
{ "9fgv0241", .driver_data = (kernel_ulong_t)&renesas_9fgv0241_info },
{ "9fgv0441", .driver_data = (kernel_ulong_t)&renesas_9fgv0441_info },
+ { "9fgv0841", .driver_data = (kernel_ulong_t)&renesas_9fgv0841_info },
{ }
};
MODULE_DEVICE_TABLE(i2c, rs9_id);
@@ -401,6 +410,7 @@ MODULE_DEVICE_TABLE(i2c, rs9_id);
static const struct of_device_id clk_rs9_of_match[] = {
{ .compatible = "renesas,9fgv0241", .data = &renesas_9fgv0241_info },
{ .compatible = "renesas,9fgv0441", .data = &renesas_9fgv0441_info },
+ { .compatible = "renesas,9fgv0841", .data = &renesas_9fgv0841_info },
{ }
};
MODULE_DEVICE_TABLE(of, clk_rs9_of_match);
--
2.42.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* RE: [PATCH v2 4/4] clk: rs9: Add support for 9FGV0841
2023-11-11 16:07 ` [PATCH v2 4/4] clk: rs9: Add support for 9FGV0841 Marek Vasut
@ 2023-11-11 16:49 ` Biju Das
0 siblings, 0 replies; 8+ messages in thread
From: Biju Das @ 2023-11-11 16:49 UTC (permalink / raw)
To: Marek Vasut, linux-clk@vger.kernel.org
Cc: Alexander Stein, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Michael Turquette, Rob Herring, Stephen Boyd,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Hi Marek Vasut,
Thanks for the patch.
> Subject: [PATCH v2 4/4] clk: rs9: Add support for 9FGV0841
>
> This model is similar to 9FGV0441, the DIFx bits start at bit 0 again,
> except this chip has 8 outputs.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Cheers,
Biju
> ---
> Cc: Alexander Stein <alexander.stein@ew.tq-group.com>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-renesas-soc@vger.kernel.org
> ---
> V2: Update on top of 2/4 and 3/4
> ---
> drivers/clk/clk-renesas-pcie.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-
> pcie.c index 5064016afbc3..6d494e5f8fa7 100644
> --- a/drivers/clk/clk-renesas-pcie.c
> +++ b/drivers/clk/clk-renesas-pcie.c
> @@ -7,6 +7,7 @@
> * Currently supported:
> * - 9FGV0241
> * - 9FGV0441
> + * - 9FGV0841
> *
> * Copyright (C) 2022 Marek Vasut <marex@denx.de>
> */
> @@ -54,6 +55,7 @@
> enum rs9_model {
> RENESAS_9FGV0241,
> RENESAS_9FGV0441,
> + RENESAS_9FGV0841,
> };
>
> /* Structure to describe features of a particular 9-series model */ @@ -
> 391,9 +393,16 @@ static const struct rs9_chip_info renesas_9fgv0441_info =
> {
> .did = RS9_REG_DID_TYPE_FGV | 0x04,
> };
>
> +static const struct rs9_chip_info renesas_9fgv0841_info = {
> + .num_clks = 8,
> + .outshift = 0,
> + .did = RS9_REG_DID_TYPE_FGV | 0x08,
> +};
> +
> static const struct i2c_device_id rs9_id[] = {
> { "9fgv0241", .driver_data =
> (kernel_ulong_t)&renesas_9fgv0241_info },
> { "9fgv0441", .driver_data =
> (kernel_ulong_t)&renesas_9fgv0441_info },
> + { "9fgv0841", .driver_data =
> (kernel_ulong_t)&renesas_9fgv0841_info },
> { }
> };
> MODULE_DEVICE_TABLE(i2c, rs9_id);
> @@ -401,6 +410,7 @@ MODULE_DEVICE_TABLE(i2c, rs9_id); static const struct
> of_device_id clk_rs9_of_match[] = {
> { .compatible = "renesas,9fgv0241", .data =
> &renesas_9fgv0241_info },
> { .compatible = "renesas,9fgv0441", .data =
> &renesas_9fgv0441_info },
> + { .compatible = "renesas,9fgv0841", .data =
> &renesas_9fgv0841_info },
> { }
> };
> MODULE_DEVICE_TABLE(of, clk_rs9_of_match);
> --
> 2.42.0
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