From: Marek Vasut <marek.vasut+renesas@mailbox.org>
To: linux-clk@vger.kernel.org
Cc: Marek Vasut <marek.vasut+renesas@mailbox.org>,
Alexander Stein <alexander.stein@ew.tq-group.com>,
Conor Dooley <conor+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: [PATCH v2 3/4] clk: rs9: Replace model check with bitshift from chip data
Date: Sat, 11 Nov 2023 17:07:01 +0100 [thread overview]
Message-ID: <20231111160806.32954-3-marek.vasut+renesas@mailbox.org> (raw)
In-Reply-To: <20231111160806.32954-1-marek.vasut+renesas@mailbox.org>
Adjust rs9_calc_dif() to special-case the 9FGV0241 where DIFx bits
start at 1, encode this shift into chip data and drop the model
check entirely.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Alexander Stein <alexander.stein@ew.tq-group.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
V2: New patch
---
drivers/clk/clk-renesas-pcie.c | 20 +++++++++-----------
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c
index b5c430e4899c..5064016afbc3 100644
--- a/drivers/clk/clk-renesas-pcie.c
+++ b/drivers/clk/clk-renesas-pcie.c
@@ -58,8 +58,8 @@ enum rs9_model {
/* Structure to describe features of a particular 9-series model */
struct rs9_chip_info {
- const enum rs9_model model;
unsigned int num_clks;
+ u8 outshift;
u8 did;
};
@@ -161,14 +161,12 @@ static const struct regmap_config rs9_regmap_config = {
static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx)
{
- enum rs9_model model = rs9->chip_info->model;
-
- if (model == RENESAS_9FGV0241)
- return BIT(idx + 1);
- else if (model == RENESAS_9FGV0441)
- return BIT(idx);
-
- return 0;
+ /*
+ * On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE(1) is BIT(2),
+ * on 9FGV0441 and 9FGV0841 the DIF OE0 is BIT(0) and so on.
+ * Increment the index in the 9FGV0241 special case here.
+ */
+ return BIT(idx + rs9->chip_info->outshift);
}
static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx)
@@ -382,14 +380,14 @@ static int __maybe_unused rs9_resume(struct device *dev)
}
static const struct rs9_chip_info renesas_9fgv0241_info = {
- .model = RENESAS_9FGV0241,
.num_clks = 2,
+ .outshift = 1,
.did = RS9_REG_DID_TYPE_FGV | 0x02,
};
static const struct rs9_chip_info renesas_9fgv0441_info = {
- .model = RENESAS_9FGV0441,
.num_clks = 4,
+ .outshift = 0,
.did = RS9_REG_DID_TYPE_FGV | 0x04,
};
--
2.42.0
next prev parent reply other threads:[~2023-11-11 16:08 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-11 16:06 [PATCH v2 1/4] dt-bindings: clk: rs9: Add 9FGV0841 Marek Vasut
2023-11-11 16:07 ` [PATCH v2 2/4] clk: rs9: Limit check to vendor ID in VID register Marek Vasut
2023-11-11 16:51 ` Biju Das
2023-11-11 16:07 ` Marek Vasut [this message]
2023-11-11 16:14 ` [PATCH v2 3/4] clk: rs9: Replace model check with bitshift from chip data Biju Das
2023-11-11 16:18 ` Marek Vasut
2023-11-11 16:07 ` [PATCH v2 4/4] clk: rs9: Add support for 9FGV0841 Marek Vasut
2023-11-11 16:49 ` Biju Das
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