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From: Rob Herring <robh@kernel.org>
To: Chen Wang <unicornxw@gmail.com>
Cc: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
	palmer@dabbelt.com, paul.walmsley@sifive.com,
	richardcochran@gmail.com, sboyd@kernel.org,
	devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com,
	Chen Wang <unicorn_wang@outlook.com>
Subject: Re: [PATCH 3/5] dt-bindings: clock: sophgo: Add SG2042 bindings
Date: Thu, 16 Nov 2023 12:18:47 -0600	[thread overview]
Message-ID: <20231116181847.GA2659392-robh@kernel.org> (raw)
In-Reply-To: <1e5836360485b63e15bdf58da59e83139666b290.1699879741.git.unicorn_wang@outlook.com>

On Mon, Nov 13, 2023 at 09:19:31PM +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
> 
> Add bindings for the clock generator on the SG2042 RISC-V SoC.
> 
> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
> ---
>  .../clock/sophgo/sophgo,sg2042-clkgen.yaml    | 48 +++++++++++++++++++
>  1 file changed, 48 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml
> new file mode 100644
> index 000000000000..e372d5dca5b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml
> @@ -0,0 +1,48 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/sophgo/sophgo,sg2042-clkgen.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Sophgo SG2042 Clock Generator
> +
> +maintainers:
> +  - Chen Wang <unicorn_wang@outlook.com>
> +
> +properties:
> +  compatible:
> +    const: sophgo,sg2042-clkgen
> +
> +  system-ctrl:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: phandle to System Register Controller syscon node.
> +    description:
> +      The phandle to System Register Controller syscon node.

Forget what I just said about syscon.yaml...

You don't need a phandle here. Just make this node a child of the 
syscon. However, why do you need a child at all? Just add 'clocks' and 
'#clock-cells' to the parent directly. You don't need a child node when 
there's only 1 child node. Maybe there's other functions, but I have no 
visibility into that. IOW, define what all the functions are so we can 
provide better guidance.

Rob

  reply	other threads:[~2023-11-16 18:18 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-13 13:16 [PATCH 0/5] riscv: sophgo: add clock support for sg2042 Chen Wang
2023-11-13 13:18 ` [PATCH 1/5] dt-bindings: clock: sophgo: Add SG2042 clock definitions Chen Wang
2023-11-14 17:35   ` Conor Dooley
2023-11-15  1:12     ` Chen Wang
2023-11-13 13:19 ` [PATCH 2/5] dt-bindings: soc: sophgo: Add Sophgo syscon module Chen Wang
2023-11-14 17:40   ` Conor Dooley
2023-11-15  1:27     ` Chen Wang
2023-11-16 18:13     ` Rob Herring
2023-11-13 13:19 ` [PATCH 3/5] dt-bindings: clock: sophgo: Add SG2042 bindings Chen Wang
2023-11-16 18:18   ` Rob Herring [this message]
2023-11-17  0:34     ` Chen Wang
2023-11-13 13:19 ` [PATCH 4/5] clk: sophgo: Add SG2042 clock generator driver Chen Wang
2023-11-15 13:02   ` kernel test robot
2023-11-19 11:11   ` kernel test robot
2023-11-13 13:20 ` [PATCH 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC Chen Wang
2023-11-14 17:31   ` Conor Dooley
2023-11-15  1:34     ` Chen Wang
2023-11-15  2:15       ` Samuel Holland
2023-11-15  2:34         ` Chen Wang

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