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From: Manivannan Sadhasivam <mani@kernel.org>
To: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Cc: agross@kernel.org, andersson@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
	konrad.dybcio@linaro.org, robh+dt@kernel.org,
	quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com,
	quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com,
	dmitry.baryshkov@linaro.org, robh@kernel.org,
	quic_krichai@quicinc.com, quic_vbadigan@quicinc.com,
	quic_parass@quicinc.com, quic_schintav@quicinc.com,
	quic_shijjose@quicinc.com,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v3 1/3] PCI: qcom: Enable cache coherency for SA8775P RC
Date: Fri, 17 Nov 2023 13:49:24 +0530	[thread overview]
Message-ID: <20231117081924.GG10361@thinkpad> (raw)
In-Reply-To: <1700051821-1087-2-git-send-email-quic_msarkar@quicinc.com>

On Wed, Nov 15, 2023 at 06:06:59PM +0530, Mrinmay Sarkar wrote:
> This change will enable cache snooping logic to support
> cache coherency for 8775 RC platform.
> 

Please add information on why the cache snoop logic is enabled only on this
platform. You have added info in the cover letter, but that's not going to be
part of the git history.

- Mani

> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 6902e97..b82ccd1 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -51,6 +51,7 @@
>  #define PARF_SID_OFFSET				0x234
>  #define PARF_BDF_TRANSLATE_CFG			0x24c
>  #define PARF_SLV_ADDR_SPACE_SIZE		0x358
> +#define PCIE_PARF_NO_SNOOP_OVERIDE		0x3d4
>  #define PARF_DEVICE_TYPE			0x1000
>  #define PARF_BDF_TO_SID_TABLE_N			0x2000
>  
> @@ -117,6 +118,10 @@
>  /* PARF_LTSSM register fields */
>  #define LTSSM_EN				BIT(8)
>  
> +/* PARF_NO_SNOOP_OVERIDE register fields */
> +#define WR_NO_SNOOP_OVERIDE_EN			BIT(1)
> +#define RD_NO_SNOOP_OVERIDE_EN			BIT(3)
> +
>  /* PARF_DEVICE_TYPE register fields */
>  #define DEVICE_TYPE_RC				0x4
>  
> @@ -961,6 +966,14 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
>  
>  static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
>  {
> +	struct dw_pcie *pci = pcie->pci;
> +	struct device *dev = pci->dev;
> +
> +	/* Enable cache snooping for SA8775P */
> +	if (of_device_is_compatible(dev->of_node, "qcom,pcie-sa8775p"))
> +		writel(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN,
> +				pcie->parf + PCIE_PARF_NO_SNOOP_OVERIDE);
> +
>  	qcom_pcie_clear_hpc(pcie->pci);
>  
>  	return 0;
> -- 
> 2.7.4
> 

-- 
மணிவண்ணன் சதாசிவம்

  parent reply	other threads:[~2023-11-17  8:19 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-15 12:36 [PATCH v3 0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P Mrinmay Sarkar
2023-11-15 12:36 ` [PATCH v3 1/3] PCI: qcom: Enable cache coherency for SA8775P RC Mrinmay Sarkar
2023-11-15 13:18   ` Dmitry Baryshkov
2023-11-15 13:21     ` Dmitry Baryshkov
2023-11-17  8:10       ` Manivannan Sadhasivam
2023-11-17  8:19   ` Manivannan Sadhasivam [this message]
2023-11-15 12:37 ` [PATCH v3 2/3] PCI: qcom-ep: Enable cache coherency for SA8775P EP Mrinmay Sarkar
2023-11-17  9:05   ` Manivannan Sadhasivam
2023-11-15 12:37 ` [PATCH v3 3/3] arm64: dts: qcom: sa8775p: Mark PCIe controller as cache coherent Mrinmay Sarkar
2023-11-17  9:06   ` Manivannan Sadhasivam
2023-11-21 14:36     ` Mrinmay Sarkar

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