From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C63130326 for ; Mon, 20 Nov 2023 18:23:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="o6e+CUPF" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3CA3EC433C7; Mon, 20 Nov 2023 18:23:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1700504629; bh=eglYaIQ/qtU51O7/Tl79eYRTbxeBJ9UX1J/7CgEKMp8=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=o6e+CUPFOXvGngNNWHM9X1PLe9PzMUguk0FCo6af1DPRNJ0p+OepiuLwS7AR5KlZ2 eakxW+7UEsZuUod6rTu0DKOh7tcfLE6bXTYE1iw3n/kMBFk0UbajUZeu6GoDKN4M3t VKhbtXzLK8ghNFU2I80Ncclrv5FKPKqgNxX/uI8+GAcwxlrDTuCohrSL3cZXDsgQcM wfpZhvWCvQUwMyN5tVCbMHPHMO22NWWBh9SCrOW4Rm9IAgoZ21fzobRc2A7iGXkhlt Y8PjAxr6YZq527RKNFptB80cmQq4RqGgqe6c29UD1Rf03Dz1U8hq9rxNYpyS2+eb3Q eYQMD4+/wUcjg== Date: Mon, 20 Nov 2023 12:23:47 -0600 From: Bjorn Helgaas To: Minda Chen Cc: Conor Dooley , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Daire McNamara , Emil Renner Berthing , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie Subject: Re: [PATCH v11 19/20] PCI: starfive: Add JH7110 PCIe controller Message-ID: <20231120182347.GA207554@bhelgaas> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3c69c1b5-7183-4d34-9689-27cd126a4f4c@starfivetech.com> On Mon, Nov 20, 2023 at 06:07:31PM +0800, Minda Chen wrote: > On 2023/11/15 19:49, Minda Chen wrote: > > Add StarFive JH7110 SoC PCIe controller platform driver codes, JH7110 > > with PLDA host PCIe core. > ... > > --- a/drivers/pci/pci.h > > +++ b/drivers/pci/pci.h > > @@ -22,6 +22,13 @@ > > */ > > #define PCIE_PME_TO_L2_TIMEOUT_US 10000 > > > > +/* > > + * PCIe r6.0, sec 6.6.1, > > + * Requires a minimum waiting of 100ms before sending a configuration > > + * request to the device. > > + */ > > +#define PCIE_BEFORE_CONFIG_REQUEST_WAIT_MS 100 > > + > > extern const unsigned char pcie_link_speed[]; > > extern bool pci_early_dump; > > > Hi Bjorn > I have not checked this carefully. > I think the change of pci.h should be moved to a indepent patch. > Could you approve this? Kevin will commit a new patch for this. > Next version I will remove this change. Yes, I think it makes sense to add that #define in a separate patch. Please trim out the unnecessary context; there's no need for readers to scroll through the entire driver to get to the useful part, which is just the last dozen lines or so. Bjorn