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From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <acme@kernel.org>, <adrian.hunter@intel.com>,
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Subject: [PATCH v4 02/13] irqchip/riscv-intc: Allow large non-standard interrupt number
Date: Wed, 22 Nov 2023 20:12:24 +0800	[thread overview]
Message-ID: <20231122121235.827122-3-peterlin@andestech.com> (raw)
In-Reply-To: <20231122121235.827122-1-peterlin@andestech.com>

Currently, the implementation of the RISC-V INTC driver uses the
interrupt cause as hwirq and has a limitation of supporting a
maximum of 64 hwirqs. However, according to the privileged spec,
interrupt causes >= 16 are defined for platform use.

This limitation prevents us from fully utilizing the available
local interrupt sources. Additionally, the hwirqs used on RISC-V
are sparse, with only interrupt numbers 1, 5 and 9 (plus Sscofpmf
or T-Head's PMU irq) being currently used for supervisor mode.

Switch to using irq_domain_create_tree() to create the radix tree
map, so a larger number of hardware interrupts can be handled.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
  - Fixed irq mapping failure checking (suggested by Clément and Anup)
Changes v2 -> v3:
  - No change
Changes v3 -> v4: (Suggested by Thomas [1])
  - Use pr_warn_ratelimited instead
  - Fix coding style and commit message

[1] https://patchwork.kernel.org/project/linux-riscv/patch/20231023004100.2663486-3-peterlin@andestech.com/#25573085
---
 drivers/irqchip/irq-riscv-intc.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index e8d01b14ccdd..2fdd40f2a791 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -24,10 +24,9 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
 {
 	unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
 
-	if (unlikely(cause >= BITS_PER_LONG))
-		panic("unexpected interrupt cause");
-
-	generic_handle_domain_irq(intc_domain, cause);
+	if (generic_handle_domain_irq(intc_domain, cause))
+		pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n",
+				    cause);
 }
 
 /*
@@ -117,8 +116,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
 {
 	int rc;
 
-	intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
-					       &riscv_intc_domain_ops, NULL);
+	intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
 	if (!intc_domain) {
 		pr_err("unable to add IRQ domain\n");
 		return -ENXIO;
@@ -132,8 +130,6 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
 
 	riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
 
-	pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
-
 	return 0;
 }
 
-- 
2.34.1


  parent reply	other threads:[~2023-11-22 12:18 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-22 12:12 [PATCH v4 00/13] Support Andes PMU extension Yu Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 01/13] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-11-24 14:57   ` Lad, Prabhakar
2023-11-22 12:12 ` Yu Chien Peter Lin [this message]
2023-12-08 15:54   ` [PATCH v4 02/13] irqchip/riscv-intc: Allow large non-standard interrupt number Thomas Gleixner
2023-12-12 10:17     ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 03/13] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2023-12-08 16:01   ` Thomas Gleixner
2023-12-12 10:28     ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-11-23 14:38   ` Conor Dooley
2023-11-24 15:03   ` Lad, Prabhakar
2023-11-24 15:05     ` Conor Dooley
2023-11-29  6:43     ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-11-22 16:36   ` Geert Uytterhoeven
2023-11-24 15:04   ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 06/13] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 07/13] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2023-11-22 21:16   ` Guo Ren
2023-11-23 14:45   ` Conor Dooley
2023-11-22 12:12 ` [PATCH v4 08/13] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2023-11-24 15:06   ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 09/13] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2023-11-22 21:14   ` Guo Ren
2023-11-29  8:48     ` Yu-Chien Peter Lin
2023-11-30  8:29       ` Inochi Amaoto
2023-11-30  9:21         ` Yu-Chien Peter Lin
2023-11-30 12:16           ` Inochi Amaoto
2023-11-30 12:58             ` Conor Dooley
2023-11-30 23:11               ` Inochi Amaoto
2023-12-01  0:40                 ` Conor Dooley
2023-12-01  0:57                   ` Inochi Amaoto
2023-12-01  1:14           ` Inochi Amaoto
2023-12-06  3:14             ` Yu-Chien Peter Lin
2023-11-23 14:48   ` Conor Dooley
2023-11-29  8:47     ` Yu-Chien Peter Lin
2023-11-29 12:33       ` Conor Dooley
2023-11-22 12:12 ` [PATCH v4 10/13] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2023-11-24 15:07   ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 11/13] riscv: dts: allwinner: Add T-Head PMU extension Yu Chien Peter Lin
2023-11-22 21:12   ` Guo Ren
2023-11-23 14:58   ` Conor Dooley
2023-11-29  9:34     ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 12/13] riscv: dts: renesas: Add Andes " Yu Chien Peter Lin
2023-11-22 16:34   ` Geert Uytterhoeven
2023-11-24 15:07   ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 13/13] riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin
2023-11-24 15:08   ` Lad, Prabhakar

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