From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="RTfTRVsi" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E52E819D; Wed, 22 Nov 2023 06:14:49 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id E09E7E0012; Wed, 22 Nov 2023 14:14:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1700662488; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4r8AmM7mXWeipOMUfi50m9Hi0q6kLe/5x9Q/douM3aY=; b=RTfTRVsisHRP5wcG9YOUbabpkm1gdgR9IUrxZ2EuBPNx1Y6drFoUm0Axd70PVxqBBTvE/c bcYl0hPsvjHoMMhJbRuIZMb7jn3OolmyCk+6ZFH3N3K547Ib+BFLG7vwc8wmHXRPToW6fi R1oR+So8dr6Ie2ALrCBshOGRR6wOm9JsQoVV5DNXL9TPBuCgVQ301ivNTsh/goID1r3QQA /pWJXv/XTs3U3BCEB/QRlDFu1dIMZq+PdAsXjlmNN5d1SYbzXp5wvyX1SIus2FIlMbsGY0 GALU9Cljj/HOQuklGq5goKsA2R1qvRXJoBOH4lkHWdQgcBFhox+I5VQ5G2Pzzw== From: Paul Kocialkowski To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Laurent Pinchart , Michael Turquette , Stephen Boyd , Paul Kocialkowski Subject: [PATCH v7 3/7] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support Date: Wed, 22 Nov 2023 15:14:21 +0100 Message-ID: <20231122141426.329694-4-paul.kocialkowski@bootlin.com> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231122141426.329694-1-paul.kocialkowski@bootlin.com> References: <20231122141426.329694-1-paul.kocialkowski@bootlin.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-GND-Sasl: paul.kocialkowski@bootlin.com MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge controller. The controller uses a separate D-PHY, which is the same that is otherwise used for MIPI DSI, but used in Rx mode. On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does not have access to any parallel interface pins. Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to support the MIPI CSI-2 interface. Note that a fwnode graph link is created between CSI0 and MIPI CSI-2 even when no sensor is connected. This will result in a probe failure for the controller as long as no sensor is connected but this is fine since no other interface is available. The interconnects property is used to inherit the proper DMA offset. Signed-off-by: Paul Kocialkowski --- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi index 506e98f4f69d..d57612023aa4 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi @@ -621,6 +621,77 @@ gic: interrupt-controller@1c81000 { interrupts = ; }; + csi0: camera@1cb0000 { + compatible = "allwinner,sun8i-v3s-csi"; + reg = <0x01cb0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + interconnects = <&mbus 5>; + interconnect-names = "dma-mem"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csi0_in_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_out_csi0>; + }; + }; + }; + }; + + mipi_csi2: csi@1cb1000 { + compatible = "allwinner,sun8i-v3s-mipi-csi2", + "allwinner,sun6i-a31-mipi-csi2"; + reg = <0x01cb1000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI1_SCLK>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + + phys = <&dphy>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_in: port@0 { + reg = <0>; + }; + + mipi_csi2_out: port@1 { + reg = <1>; + + mipi_csi2_out_csi0: endpoint { + remote-endpoint = <&csi0_in_mipi_csi2>; + }; + }; + }; + }; + + dphy: d-phy@1cb2000 { + compatible = "allwinner,sun6i-a31-mipi-dphy"; + reg = <0x01cb2000 0x1000>; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_MIPI_CSI>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CSI>; + allwinner,direction = "rx"; + status = "disabled"; + #phy-cells = <0>; + }; + csi1: camera@1cb4000 { compatible = "allwinner,sun8i-v3s-csi"; reg = <0x01cb4000 0x3000>; -- 2.42.1