From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="sDY2cKHY" Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E04DAD40; Thu, 23 Nov 2023 06:47:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1700750848; x=1732286848; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=MUsg89fQ9NBzKyUbXc1Aej1I5ZOvhdvSHAYt6cV/nr8=; b=sDY2cKHYA7Ur/S9Ne2KmDFGXmc/SWRnf2vwqOYIdtA3mKzlp8VomzHiQ 18n7DDHm3LOoA0H0lDy42kcXyM5/LZM42fbGuXBLDxXONG1Y71C8ed383 TJyQf/FtGxStkWmJUb3TlQUSdq6xLhOXcelC7fj3QUgFtz7NnoHiel7IU 4/hPCg0I97YTMwOklmlqvQUPDXZbytrTzzGMvPv6wFoQlRaobD5tKqc72 M2jRMn4lPbVU55Fv9eeTeE6VueHdmDuNOORF6CjtAdrbi4/ZKJqvIJDfB dn1lOFYQM9G3kV1IlhsuWu8oTGW/G6QMdXQFamcUDC0+vVFTk4qWGEkLq w==; X-CSE-ConnectionGUID: BE0Y80HqR8yoj+GuwVwALQ== X-CSE-MsgGUID: b3thrMNzRuC8XgsnWxRyVw== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.04,222,1695711600"; d="asc'?scan'208";a="12195934" X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Nov 2023 07:47:26 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 23 Nov 2023 07:46:36 -0700 Received: from wendy (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21 via Frontend Transport; Thu, 23 Nov 2023 07:46:27 -0700 Date: Thu, 23 Nov 2023 14:45:59 +0000 From: Conor Dooley To: Yu Chien Peter Lin CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v4 07/13] RISC-V: Move T-Head PMU to CPU feature alternative framework Message-ID: <20231123-snub-headdress-23a80f001ccd@wendy> References: <20231122121235.827122-1-peterlin@andestech.com> <20231122121235.827122-8-peterlin@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="u2td/6ehnVJK/j3z" Content-Disposition: inline In-Reply-To: <20231122121235.827122-8-peterlin@andestech.com> --u2td/6ehnVJK/j3z Content-Type: text/plain; charset=us-ascii Content-Disposition: inline > drivers/perf/riscv_pmu_sbi.c | 19 ++++++++++++++----- > +config THEAD_CUSTOM_PMU > + bool "T-Head custom PMU support" > + depends on RISCV_ALTERNATIVE && RISCV_PMU_SBI > + default y > + help > + The T-Head C9xx cores implement a PMU overflow extension very > + similar to the core SSCOFPMF extension. > + > + This will patch the overflow CSR and handle the non-standard > + behaviour via the regular SBI PMU driver and interface. > + > + If you don't know what to do here, say "Y". This is a < 20 line diff to the pmu driver, is it really worth adding having config options for these two non standard PMU implementations? --u2td/6ehnVJK/j3z Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZV9lpwAKCRB4tDGHoIJi 0p2/AP44N1mho7QcO/007yqDwBgkqYEOvZh2Uuy27l3ZNMV4CwD7BXD0U3yWECON 6d7xv7JjsIfKlCFpYK59CusQR3peRg0= =tcdb -----END PGP SIGNATURE----- --u2td/6ehnVJK/j3z--