* [PATCH v2 01/10] arm64: dts: rockchip: Drop edgeble-neu6b dcdc-reg4 regulator-init-microvolt
2023-11-25 19:05 [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT Jagan Teki
@ 2023-11-25 19:05 ` Jagan Teki
2023-11-25 19:05 ` [PATCH v2 02/10] arm64: dts: rockchip: Add edgeble-neu6a-common DT Jagan Teki
` (10 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jagan Teki @ 2023-11-25 19:05 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-arm-kernel, linux-rockchip, Jagan Teki
The 'regulator-init-microvolt' property is not currently supported by
any driver, it was simply carried on from downstream kernels.
rk3588-edgeble-neu6b-io.dtb: pmic@0: regulators:dcdc-reg4: Unevaluated properties are not allowed ('regulator-init-microvolt' was unexpected)
Remove the invalid property.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v2:
- none
arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi
index 017559bba37f..4797260a8a78 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi
@@ -165,7 +165,6 @@ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
- regulator-init-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-state-mem {
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 02/10] arm64: dts: rockchip: Add edgeble-neu6a-common DT
2023-11-25 19:05 [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT Jagan Teki
2023-11-25 19:05 ` [PATCH v2 01/10] arm64: dts: rockchip: Drop edgeble-neu6b dcdc-reg4 regulator-init-microvolt Jagan Teki
@ 2023-11-25 19:05 ` Jagan Teki
2023-11-25 19:05 ` [PATCH v2 03/10] arm64: dts: rockchip: Add common DT for edgeble-neu6b-io Jagan Teki
` (9 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jagan Teki @ 2023-11-25 19:05 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-arm-kernel, linux-rockchip, Jagan Teki
Edgeble NCM6A-IO is common compatible IO board for both NCM6A
and NCM6B. Add a common io DTSI for it to include them in both
NCM6A and NCM6B DTS files.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v2:
- none
.../rockchip/rk3588-edgeble-neu6a-common.dtsi | 386 ++++++++++++++++++
.../dts/rockchip/rk3588-edgeble-neu6a.dtsi | 25 +-
.../dts/rockchip/rk3588-edgeble-neu6b.dtsi | 382 +----------------
3 files changed, 390 insertions(+), 403 deletions(-)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
new file mode 100644
index 000000000000..e141dc84654a
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
@@ -0,0 +1,386 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/ {
+ aliases {
+ mmc0 = &sdhci;
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
+
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-name = "vdd_log_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-name = "avcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-name = "avdd_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdd_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-name = "avdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-name = "vdd_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-name = "vdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi
index 727580aaa105..4c76a00b41eb 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi
@@ -3,29 +3,8 @@
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
+#include "rk3588-edgeble-neu6a-common.dtsi"
+
/ {
compatible = "edgeble,neural-compute-module-6a", "rockchip,rk3588";
-
- aliases {
- mmc0 = &sdhci;
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-};
-
-&sdhci {
- bus-width = <8>;
- no-sdio;
- no-sd;
- non-removable;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi
index 4797260a8a78..c4634bc09fb4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi
@@ -3,386 +3,8 @@
* Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
*/
+#include "rk3588-edgeble-neu6a-common.dtsi"
+
/ {
compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588";
-
- aliases {
- mmc0 = &sdhci;
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v1_nldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&sdhci {
- bus-width = <8>;
- no-sdio;
- no-sd;
- non-removable;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- status = "okay";
-};
-
-&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- num-cs = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
-
- pmic@0 {
- compatible = "rockchip,rk806";
- spi-max-frequency = <1000000>;
- reg = <0x0>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc5v0_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc5v0_sys>;
- vcc13-supply = <&vcc_1v1_nldo_s3>;
- vcc14-supply = <&vcc_1v1_nldo_s3>;
- vcca-supply = <&vcc5v0_sys>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs2_null: dvs2-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs3_null: dvs3-null-pins {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- regulators {
- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
- regulator-name = "vdd_gpu_s0";
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-enable-ramp-delay = <400>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
- regulator-name = "vdd_cpu_lit_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_log_s0: dcdc-reg3 {
- regulator-name = "vdd_log_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
- regulator-name = "vdd_vdenc_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_s0: dcdc-reg5 {
- regulator-name = "vdd_ddr_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <900000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- vdd2_ddr_s3: dcdc-reg6 {
- regulator-name = "vdd2_ddr_s3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_2v0_pldo_s3: dcdc-reg7 {
- regulator-name = "vdd_2v0_pldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2000000>;
- };
- };
-
- vcc_3v3_s3: dcdc-reg8 {
- regulator-name = "vcc_3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vddq_ddr_s0: dcdc-reg9 {
- regulator-name = "vddq_ddr_s0";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s3: dcdc-reg10 {
- regulator-name = "vcc_1v8_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avcc_1v8_s0: pldo-reg1 {
- regulator-name = "avcc_1v8_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s0: pldo-reg2 {
- regulator-name = "vcc_1v8_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avdd_1v2_s0: pldo-reg3 {
- regulator-name = "avdd_1v2_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s0: pldo-reg4 {
- regulator-name = "vcc_3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd_s0: pldo-reg5 {
- regulator-name = "vccio_sd_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- pldo6_s3: pldo-reg6 {
- regulator-name = "pldo6_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_s3: nldo-reg1 {
- regulator-name = "vdd_0v75_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_ddr_pll_s0: nldo-reg2 {
- regulator-name = "vdd_ddr_pll_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- avdd_0v75_s0: nldo-reg3 {
- regulator-name = "avdd_0v75_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v85_s0: nldo-reg4 {
- regulator-name = "vdd_0v85_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v75_s0: nldo-reg5 {
- regulator-name = "vdd_0v75_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
};
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 03/10] arm64: dts: rockchip: Add common DT for edgeble-neu6b-io
2023-11-25 19:05 [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT Jagan Teki
2023-11-25 19:05 ` [PATCH v2 01/10] arm64: dts: rockchip: Drop edgeble-neu6b dcdc-reg4 regulator-init-microvolt Jagan Teki
2023-11-25 19:05 ` [PATCH v2 02/10] arm64: dts: rockchip: Add edgeble-neu6a-common DT Jagan Teki
@ 2023-11-25 19:05 ` Jagan Teki
2023-11-25 19:05 ` [PATCH v2 04/10] arm64: dts: rockchip: Add Edgeble NCM6A WiFi6 Overlay Jagan Teki
` (8 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jagan Teki @ 2023-11-25 19:05 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-arm-kernel, linux-rockchip, Jagan Teki
Edgeble Neu6a and Neu6b are compatible with common IO board.
So, maintain the IO board in rk3588-edgeble-neu6a-io.dtsi.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v2:
- none
.../dts/rockchip/rk3588-edgeble-neu6a-io.dts | 14 +--
.../dts/rockchip/rk3588-edgeble-neu6a-io.dtsi | 85 +++++++++++++++++++
.../dts/rockchip/rk3588-edgeble-neu6b-io.dts | 80 +----------------
3 files changed, 87 insertions(+), 92 deletions(-)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts
index b51543892078..46d5e21d4d27 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts
@@ -6,22 +6,10 @@
/dts-v1/;
#include "rk3588.dtsi"
#include "rk3588-edgeble-neu6a.dtsi"
+#include "rk3588-edgeble-neu6a-io.dtsi"
/ {
model = "Edgeble Neu6A IO Board";
compatible = "edgeble,neural-compute-module-6a-io",
"edgeble,neural-compute-module-6a", "rockchip,rk3588";
-
- aliases {
- serial2 = &uart2;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
new file mode 100644
index 000000000000..845f90c302ca
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/ {
+ aliases {
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ wakeup-source;
+ };
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+/* FAN */
+&pwm2 {
+ pinctrl-0 = <&pwm2m1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+/* RS232 */
+&uart6 {
+ pinctrl-0 = <&uart6m0_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/* RS485 */
+&uart7 {
+ pinctrl-0 = <&uart7m2_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts
index 861067b5d707..0d6f1be69ac8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts
@@ -6,88 +6,10 @@
/dts-v1/;
#include "rk3588j.dtsi"
#include "rk3588-edgeble-neu6b.dtsi"
+#include "rk3588-edgeble-neu6a-io.dtsi"
/ {
model = "Edgeble Neu6B IO Board";
compatible = "edgeble,neural-compute-module-6a-io",
"edgeble,neural-compute-module-6b", "rockchip,rk3588";
-
- aliases {
- serial2 = &uart2;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-};
-
-&combphy0_ps {
- status = "okay";
-};
-
-&i2c6 {
- status = "okay";
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <0>;
- clock-output-names = "hym8563";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- wakeup-source;
- };
-};
-
-&pinctrl {
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-/* FAN */
-&pwm2 {
- pinctrl-0 = <&pwm2m1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&sata0 {
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- no-sdio;
- no-mmc;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
-};
-
-/* RS232 */
-&uart6 {
- pinctrl-0 = <&uart6m0_xfer>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-/* RS485 */
-&uart7 {
- pinctrl-0 = <&uart7m2_xfer>;
- pinctrl-names = "default";
- status = "okay";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 04/10] arm64: dts: rockchip: Add Edgeble NCM6A WiFi6 Overlay
2023-11-25 19:05 [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT Jagan Teki
` (2 preceding siblings ...)
2023-11-25 19:05 ` [PATCH v2 03/10] arm64: dts: rockchip: Add common DT for edgeble-neu6b-io Jagan Teki
@ 2023-11-25 19:05 ` Jagan Teki
2023-11-25 19:05 ` [PATCH v2 05/10] arm64: dts: rockchip: Add vdd_cpu_big reg to rk3588-edgeble-ncm6 Jagan Teki
` (7 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jagan Teki @ 2023-11-25 19:05 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-arm-kernel, linux-rockchip, Jagan Teki
Edgeble NCM6A SOM has on-module M.2 1216-compatible WiFi modules.
Currently, AW-XM548NF WiFi6 and Intel 8260D2W WiFi5 modules are supported.
WiFi modules are fixed on SoM, not pluggable M.2 slots, so different SoM's
for each type of WiFi module.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v2:
- none
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../rockchip/rk3588-edgeble-neu6a-wifi.dtso | 56 +++++++++++++++++++
2 files changed, 57 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-wifi.dtso
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index f969618da352..543a2f68b654 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -100,6 +100,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-wifi.dtso b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-wifi.dtso
new file mode 100644
index 000000000000..e9a3855e8752
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-wifi.dtso
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ *
+ * DT-overlay for Edgeble On-SoM WiFi6/BT M.2 1216 modules,
+ * - AW-XM548NF
+ * - Intel 8260D2W
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+&{/} {
+ vcc3v3_pcie2x1l1: vcc3v3-pcie2x1l1-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; /* WIFI_3V3_EN */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_1_vcc3v3_en>;
+ regulator-name = "vcc3v3_pcie2x1l1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+/* WiFi6 */
+&pcie2x1l1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_1_rst>;
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; /* PCIE20_2_WIFI_PERSTn */
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l1>;
+ status = "okay";
+};
+
+&pinctrl {
+ pcie2 {
+ pcie2_1_rst: pcie2-1-rst {
+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie2_1_vcc3v3_en: pcie2-1-vcc-en {
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 05/10] arm64: dts: rockchip: Add vdd_cpu_big reg to rk3588-edgeble-ncm6
2023-11-25 19:05 [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT Jagan Teki
` (3 preceding siblings ...)
2023-11-25 19:05 ` [PATCH v2 04/10] arm64: dts: rockchip: Add Edgeble NCM6A WiFi6 Overlay Jagan Teki
@ 2023-11-25 19:05 ` Jagan Teki
2023-11-25 19:05 ` [PATCH v2 06/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO 2.5G ETH Jagan Teki
` (6 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jagan Teki @ 2023-11-25 19:05 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-arm-kernel, linux-rockchip, Jagan Teki
The RK8602 and RK8603 voltage regulators on the Rock 5B board provide
the power lines vdd_cpu_big0 and vdd_cpu_big1, respectively.
Add the necessary device tree nodes and bind them to the corresponding
CPU big core nodes.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v2:
- none
.../rockchip/rk3588-edgeble-neu6a-common.dtsi | 56 +++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
index e141dc84654a..961a80014686 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
@@ -38,6 +38,22 @@ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
};
};
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
@@ -54,6 +70,46 @@ &cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
&sdhci {
bus-width = <8>;
no-sdio;
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 06/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO 2.5G ETH
2023-11-25 19:05 [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT Jagan Teki
` (4 preceding siblings ...)
2023-11-25 19:05 ` [PATCH v2 05/10] arm64: dts: rockchip: Add vdd_cpu_big reg to rk3588-edgeble-ncm6 Jagan Teki
@ 2023-11-25 19:05 ` Jagan Teki
2023-11-25 19:05 ` [PATCH v2 07/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 M-Key Jagan Teki
` (5 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jagan Teki @ 2023-11-25 19:05 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-arm-kernel, linux-rockchip, Jagan Teki
Edgeble NCM6A-IO board has 2.5Gbps Ethernet via PCI2_0.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v2:
- none
.../dts/rockchip/rk3588-edgeble-neu6a-io.dtsi | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
index 845f90c302ca..7e838d76fa73 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
@@ -3,6 +3,8 @@
* Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
*/
+#include <dt-bindings/gpio/gpio.h>
+
/ {
aliases {
serial2 = &uart2;
@@ -11,12 +13,25 @@ aliases {
chosen {
stdout-path = "serial2:1500000n8";
};
+
+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie2x1l0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
};
&combphy0_ps {
status = "okay";
};
+&combphy1_ps {
+ status = "okay";
+};
+
&i2c6 {
status = "okay";
@@ -33,7 +48,22 @@ hym8563: rtc@51 {
};
};
+/* ETH */
+&pcie2x1l0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_0_rst>;
+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; /* PCIE20_1_PERST_L */
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
+ status = "okay";
+};
+
&pinctrl {
+ pcie2 {
+ pcie2_0_rst: pcie2-0-rst {
+ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 07/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 M-Key
2023-11-25 19:05 [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT Jagan Teki
` (5 preceding siblings ...)
2023-11-25 19:05 ` [PATCH v2 06/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO 2.5G ETH Jagan Teki
@ 2023-11-25 19:05 ` Jagan Teki
2023-11-25 19:05 ` [PATCH v2 08/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 B-Key, E-Key Jagan Teki
` (4 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jagan Teki @ 2023-11-25 19:05 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-arm-kernel, linux-rockchip, Jagan Teki
Edgeble NCM6A-IO board has M.2 M-Key via PCI3x4.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v2:
- suffix '-regulator'
- use proper node name
.../dts/rockchip/rk3588-edgeble-neu6a-io.dtsi | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
index 7e838d76fa73..088a10fe042c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
@@ -22,6 +22,19 @@ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
startup-delay-us = <5000>;
vin-supply = <&vcc_3v3_s3>;
};
+
+ vcc3v3_pcie3x4: vcc3v3-pcie3x4-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; /* PCIE30x4_PWREN_H */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3x4_vcc3v3_en>;
+ regulator-name = "vcc3v3_pcie3x4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
};
&combphy0_ps {
@@ -57,6 +70,19 @@ &pcie2x1l0 {
status = "okay";
};
+&pcie30phy {
+ status = "okay";
+};
+
+/* M-Key */
+&pcie3x4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3x4_rst>;
+ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */
+ vpcie3v3-supply = <&vcc3v3_pcie3x4>;
+ status = "okay";
+};
+
&pinctrl {
pcie2 {
pcie2_0_rst: pcie2-0-rst {
@@ -64,6 +90,16 @@ pcie2_0_rst: pcie2-0-rst {
};
};
+ pcie3 {
+ pcie3x4_rst: pcie3x4-rst {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie3x4_vcc3v3_en: pcie3x4-vcc3v3-en {
+ rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 08/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 B-Key, E-Key
2023-11-25 19:05 [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT Jagan Teki
` (6 preceding siblings ...)
2023-11-25 19:05 ` [PATCH v2 07/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 M-Key Jagan Teki
@ 2023-11-25 19:05 ` Jagan Teki
2023-11-25 19:05 ` [PATCH v2 09/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO USB2 Jagan Teki
` (3 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jagan Teki @ 2023-11-25 19:05 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-arm-kernel, linux-rockchip, Jagan Teki
Edgeble NCM6A-IO board has M.2 B-Key, E-Key via PCI3x2.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v2:
- suffix '-regulator'
- use proper node name
- fix commit head
- update comments
.../dts/rockchip/rk3588-edgeble-neu6a-io.dtsi | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
index 088a10fe042c..130b240e0da8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
@@ -23,6 +23,19 @@ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
vin-supply = <&vcc_3v3_s3>;
};
+ vcc3v3_pcie3x2: vcc3v3-pcie3x2-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_4G_PWEN */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3x2_vcc3v3_en>;
+ regulator-name = "vcc3v3_pcie3x2";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
vcc3v3_pcie3x4: vcc3v3-pcie3x4-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -74,6 +87,15 @@ &pcie30phy {
status = "okay";
};
+/* B-Key and E-Key */
+&pcie3x2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3x2_rst>;
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */
+ vpcie3v3-supply = <&vcc3v3_pcie3x2>;
+ status = "okay";
+};
+
/* M-Key */
&pcie3x4 {
pinctrl-names = "default";
@@ -91,6 +113,14 @@ pcie2_0_rst: pcie2-0-rst {
};
pcie3 {
+ pcie3x2_rst: pcie3x2-rst {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie3x2_vcc3v3_en: pcie3x2-vcc3v3-en {
+ rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
pcie3x4_rst: pcie3x4-rst {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 09/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO USB2
2023-11-25 19:05 [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT Jagan Teki
` (7 preceding siblings ...)
2023-11-25 19:05 ` [PATCH v2 08/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 B-Key, E-Key Jagan Teki
@ 2023-11-25 19:05 ` Jagan Teki
2023-11-25 19:05 ` [PATCH v2 10/10] arm64: dts: rockchip: Add LED_GREEN for edgeble-neu6a Jagan Teki
` (2 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jagan Teki @ 2023-11-25 19:05 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-arm-kernel, linux-rockchip, Jagan Teki
Edgeble NCM6A-IO board has 2 port USB2.0 Host and USB2.0 on E-Key.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v2:
- none
.../dts/rockchip/rk3588-edgeble-neu6a-io.dtsi | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
index 130b240e0da8..9b65df3398c3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
@@ -48,6 +48,20 @@ vcc3v3_pcie3x4: vcc3v3-pcie3x4-regulator {
startup-delay-us = <5000>;
vin-supply = <&vcc5v0_sys>;
};
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
};
&combphy0_ps {
@@ -135,6 +149,12 @@ hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
/* FAN */
@@ -179,3 +199,38 @@ &uart7 {
pinctrl-names = "default";
status = "okay";
};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ /* connected to USB hub, which is powered by vcc5v0_sys */
+ phy-supply = <&vcc5v0_sys>;
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 10/10] arm64: dts: rockchip: Add LED_GREEN for edgeble-neu6a
2023-11-25 19:05 [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT Jagan Teki
` (8 preceding siblings ...)
2023-11-25 19:05 ` [PATCH v2 09/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO USB2 Jagan Teki
@ 2023-11-25 19:05 ` Jagan Teki
2024-01-02 11:01 ` [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT Jagan Teki
2024-01-25 21:12 ` Heiko Stuebner
11 siblings, 0 replies; 14+ messages in thread
From: Jagan Teki @ 2023-11-25 19:05 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-arm-kernel, linux-rockchip, Jagan Teki
Edgeble NCM6A, NCM6B SoM has Green LED on the module.
Enable them with heartbeat function.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v2:
- none
.../rockchip/rk3588-edgeble-neu6a-common.dtsi | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
index 961a80014686..003887fbf996 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
@@ -3,11 +3,27 @@
* Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
*/
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
/ {
aliases {
mmc0 = &sdhci;
};
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led_user: led-0 {
+ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_user_en>;
+ };
+ };
+
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@@ -110,6 +126,14 @@ regulator-state-mem {
};
};
+&pinctrl {
+ leds {
+ led_user_en: led_user_en {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
&sdhci {
bus-width = <8>;
no-sdio;
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT
2023-11-25 19:05 [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT Jagan Teki
` (9 preceding siblings ...)
2023-11-25 19:05 ` [PATCH v2 10/10] arm64: dts: rockchip: Add LED_GREEN for edgeble-neu6a Jagan Teki
@ 2024-01-02 11:01 ` Jagan Teki
2024-01-18 7:00 ` Jagan Teki
2024-01-25 21:12 ` Heiko Stuebner
11 siblings, 1 reply; 14+ messages in thread
From: Jagan Teki @ 2024-01-02 11:01 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-arm-kernel, linux-rockchip
Hi Heiko,
On Sun, 26 Nov 2023 at 00:35, Jagan Teki <jagan@edgeble.ai> wrote:
>
> DT patch set for Edgeble NCM6A, NCM6B SoM, and IO board.
>
> Changes for v2:
> - suffix -regulator in node names
> - fix node lables
> - update commit message
>
> Any inputs?
> Jagan.
>
> Jagan Teki (10):
> arm64: dts: rockchip: Drop edgeble-neu6b dcdc-reg4 regulator-init-microvolt
> arm64: dts: rockchip: Add edgeble-neu6a-common DT
> arm64: dts: rockchip: Add common DT for edgeble-neu6b-io
> arm64: dts: rockchip: Add Edgeble NCM6A WiFi6 Overlay
> arm64: dts: rockchip: Add vdd_cpu_big reg to rk3588-edgeble-ncm6
> arm64: dts: rockchip: Add Edgeble NCM6A-IO 2.5G ETH
> arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 M-Key
> arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 B-Key, E-Key
> arm64: dts: rockchip: Add Edgeble NCM6A-IO USB2
> arm64: dts: rockchip: Add LED_GREEN for edgeble-neu6a
Any update on this patch-set?
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT
2024-01-02 11:01 ` [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT Jagan Teki
@ 2024-01-18 7:00 ` Jagan Teki
0 siblings, 0 replies; 14+ messages in thread
From: Jagan Teki @ 2024-01-18 7:00 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-arm-kernel, linux-rockchip
Hi Heiko,
On Tue, 2 Jan 2024 at 16:31, Jagan Teki <jagan@edgeble.ai> wrote:
>
> Hi Heiko,
>
> On Sun, 26 Nov 2023 at 00:35, Jagan Teki <jagan@edgeble.ai> wrote:
> >
> > DT patch set for Edgeble NCM6A, NCM6B SoM, and IO board.
> >
> > Changes for v2:
> > - suffix -regulator in node names
> > - fix node lables
> > - update commit message
> >
> > Any inputs?
> > Jagan.
> >
> > Jagan Teki (10):
> > arm64: dts: rockchip: Drop edgeble-neu6b dcdc-reg4 regulator-init-microvolt
> > arm64: dts: rockchip: Add edgeble-neu6a-common DT
> > arm64: dts: rockchip: Add common DT for edgeble-neu6b-io
> > arm64: dts: rockchip: Add Edgeble NCM6A WiFi6 Overlay
> > arm64: dts: rockchip: Add vdd_cpu_big reg to rk3588-edgeble-ncm6
> > arm64: dts: rockchip: Add Edgeble NCM6A-IO 2.5G ETH
> > arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 M-Key
> > arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 B-Key, E-Key
> > arm64: dts: rockchip: Add Edgeble NCM6A-IO USB2
> > arm64: dts: rockchip: Add LED_GREEN for edgeble-neu6a
>
> Any update on this patch-set?
Can you merge this, if it's Okay? Planning to sync the DT in U-Boot before MW.
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT
2023-11-25 19:05 [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT Jagan Teki
` (10 preceding siblings ...)
2024-01-02 11:01 ` [PATCH v2 00/10] arm64: dts: rockchip: Pack Edgeble NCM6A, 6B DT Jagan Teki
@ 2024-01-25 21:12 ` Heiko Stuebner
11 siblings, 0 replies; 14+ messages in thread
From: Heiko Stuebner @ 2024-01-25 21:12 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Jagan Teki, Conor Dooley
Cc: Heiko Stuebner, devicetree, linux-arm-kernel, linux-rockchip
On Sun, 26 Nov 2023 00:35:12 +0530, Jagan Teki wrote:
> DT patch set for Edgeble NCM6A, NCM6B SoM, and IO board.
>
> Changes for v2:
> - suffix -regulator in node names
> - fix node lables
> - update commit message
>
> [...]
Applied, thanks!
[01/10] arm64: dts: rockchip: Drop edgeble-neu6b dcdc-reg4 regulator-init-microvolt
commit: 271e4e979a5a32617fe811df8410cfc477918c68
[02/10] arm64: dts: rockchip: Add edgeble-neu6a-common DT
commit: 736e39a0af98d5dd165b8cc99837790c3e019d39
[03/10] arm64: dts: rockchip: Add common DT for edgeble-neu6b-io
commit: 40137b58e7dec7624de41b9c4c22219e230b5b99
[04/10] arm64: dts: rockchip: Add Edgeble NCM6A WiFi6 Overlay
commit: 951d6aaa37fed409c30669ddfed5d1e040cdb281
[05/10] arm64: dts: rockchip: Add vdd_cpu_big reg to rk3588-edgeble-ncm6
commit: 9f6d8911cc3b7fbe270ef991b0db0a8b623e01a9
[06/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO 2.5G ETH
commit: 8c711ff32748b46688ddc6663e377dba12ed22cd
[07/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 M-Key
commit: 5d85d4c7e03b44bc31814420bb73b2ba12e42c22
[08/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 B-Key, E-Key
commit: 92eaee21abbdf07001a7ee3c0d03c48889619600
[09/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO USB2
commit: 762751c183750243f68c1b48889d89d4653c9f19
[10/10] arm64: dts: rockchip: Add LED_GREEN for edgeble-neu6a
commit: 9b606d2d11af4b131e7a3e5889f43a193e637c66
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
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