[PATCH 1/3] arm64: dts: imx8mm: Simplify mipi_dsi clocks

[Adam Ford <aford173@gmail.com>]

The device tree clock structure for the mipi_dsi is
unnecessarily redundant.

The default clock parent of IMX8MM_CLK_DSI_PHY_REF is
already IMX8MM_CLK_24M, so there is no need to set the
parent-child relationship between them.  The default clock
rates for IMX8MM_SYS_PLL1_266M and IMX8MM_CLK_24M are
already defined to be 266MHz and 24MHz respectively,
so there is no need to define those clock rates.

On i.MX8M[MNP] the  samsung,pll-clock-frequency is not
necessary, because the driver will read it from sclk_mipi
which is also already set to 24MHz making it also
redundant.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 738024baaa57..8d872568231d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1151,12 +1151,8 @@ mipi_dsi: dsi@32e10000 {
 				clocks = <&clk IMX8MM_CLK_DSI_CORE>,
 					 <&clk IMX8MM_CLK_DSI_PHY_REF>;
 				clock-names = "bus_clk", "sclk_mipi";
-				assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
-						  <&clk IMX8MM_CLK_DSI_PHY_REF>;
-				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
-							 <&clk IMX8MM_CLK_24M>;
-				assigned-clock-rates = <266000000>, <24000000>;
-				samsung,pll-clock-frequency = <24000000>;
+				assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>;
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>;
 				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 				power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
 				status = "disabled";
-- 
2.40.1