From: Conor Dooley <conor@kernel.org>
To: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Cc: kernel@esmil.dk, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, krzk@kernel.org,
conor+dt@kernel.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu,
daniel.lezcano@linaro.org, tglx@linutronix.de,
anup@brainfault.org, gregkh@linuxfoundation.org,
jirislaby@kernel.org, michal.simek@amd.com,
michael.zhu@starfivetech.com, drew@beagleboard.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, leyfoon.tan@starfivetech.com
Subject: Re: [PATCH v2 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles
Date: Wed, 29 Nov 2023 14:45:58 +0000 [thread overview]
Message-ID: <20231129-revisit-prefix-5327168e91f3@spud> (raw)
In-Reply-To: <20231129060043.368874-2-jeeheng.sia@starfivetech.com>
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On Wed, Nov 29, 2023 at 02:00:38PM +0800, Sia Jee Heng wrote:
> Add new compatible strings for Dubhe-80 and Dubhe-90. These are
> RISC-V cpu core from StarFive Technology and are used in StarFive
> JH8100 SoC.
>
> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index f392e367d673..493972b29a22 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -48,6 +48,8 @@ properties:
> - thead,c906
> - thead,c910
> - thead,c920
> + - starfive,dubhe-80
> + - starfive,dubhe-90
s goes before t.
Cheers,
Conor.
> - const: riscv
> - items:
> - enum:
> --
> 2.34.1
>
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next prev parent reply other threads:[~2023-11-29 14:46 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-29 6:00 [PATCH v2 0/6] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng
2023-11-29 6:00 ` [PATCH v2 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles Sia Jee Heng
2023-11-29 14:45 ` Conor Dooley [this message]
2023-11-30 6:04 ` JeeHeng Sia
2023-11-30 15:08 ` Conor Dooley
2023-11-29 6:00 ` [PATCH v2 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC Sia Jee Heng
2023-11-29 8:26 ` Krzysztof Kozlowski
2023-11-29 10:35 ` JeeHeng Sia
2023-11-29 14:46 ` Conor Dooley
2023-11-29 14:47 ` Conor Dooley
2023-11-29 6:00 ` [PATCH v2 3/6] dt-bindings: timer: Add StarFive JH8100 clint Sia Jee Heng
2023-11-29 14:50 ` Conor Dooley
2023-11-29 6:00 ` [PATCH v2 4/6] dt-bindings: interrupt-controller: Add StarFive JH8100 plic Sia Jee Heng
2023-11-29 14:48 ` Conor Dooley
2023-11-29 6:00 ` [PATCH v2 5/6] dt-bindings: serial: cdns: Add new compatible string for StarFive JH8100 UART Sia Jee Heng
2023-11-29 8:26 ` Krzysztof Kozlowski
2023-11-29 10:33 ` JeeHeng Sia
2023-11-29 10:53 ` Krzysztof Kozlowski
2023-11-29 13:15 ` JeeHeng Sia
2023-11-29 6:00 ` [PATCH v2 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree Sia Jee Heng
2023-11-30 17:58 ` Leyfoon Tan
2023-12-01 1:34 ` JeeHeng Sia
2023-12-01 7:02 ` [PATCH v2 0/6] Initial device tree support for StarFive JH8100 SoC JeeHeng Sia
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