From: "Rafał Miłecki" <zajec5@gmail.com>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: "Nícolas F . R . A . Prado" <nfraprado@collabora.com>,
"Macpaul Lin" <macpaul.lin@mediatek.com>,
"Bernhard Rosenkränzer" <bero@baylibre.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Chris Morgan" <macromorgan@hotmail.com>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Sean Wang" <sean.wang@mediatek.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
"Rafał Miłecki" <rafal@milecki.pl>
Subject: [PATCH V2 3/3] arm64: dts: mediatek: Add Acelink EW-7886CAX
Date: Mon, 4 Dec 2023 21:09:07 +0100 [thread overview]
Message-ID: <20231204200907.5687-3-zajec5@gmail.com> (raw)
In-Reply-To: <20231204200907.5687-1-zajec5@gmail.com>
From: Rafał Miłecki <rafal@milecki.pl>
Acelink EW-7886CAX is an MT7986A (AKA Filogic 830) based access point.
It has 512 MiB of RAM, one 2.5 Gbps PoE (802.3at) Ethernet port and
on-SoC Wi-Fi.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
V2: Update coding style to follow:
[PATCH v4] docs: dt-bindings: add DTS Coding Style document
arch/arm64/boot/dts/mediatek/Makefile | 1 +
.../mediatek/mt7986a-acelink-ew-7886cax.dts | 173 ++++++++++++++++++
2 files changed, 174 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index e6e7592a3645..9ff2ab6c5e4d 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-acelink-ew-7886cax.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts b/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts
new file mode 100644
index 000000000000..93b71465bbdf
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+#include "mt7986a.dtsi"
+
+/ {
+ compatible = "acelink,ew-7886cax", "mediatek,mt7986a";
+ model = "Acelink EW-7886CAX";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ reg = <0 0x40000000 0 0x20000000>;
+ device_type = "memory";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ key-restart {
+ label = "Reset";
+ gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 18 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-2 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&crypto {
+ status = "okay";
+};
+
+ð {
+ status = "okay";
+
+ mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "2500base-x";
+ phy-handle = <&phy6>;
+ nvmem-cells = <&macaddr>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ mdio-bus {
+ reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <50000>;
+ reset-post-delay-us = <20000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy6: phy@6 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <6>;
+ };
+ };
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>
+ spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+
+ partitions: partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ reg = <0x0 0x100000>;
+ label = "bootloader";
+ read-only;
+ };
+
+ partition@100000 {
+ reg = <0x100000 0x80000>;
+ label = "u-boot-env";
+ };
+
+ partition@180000 {
+ compatible = "nvmem-cells";
+ reg = <0x180000 0x200000>;
+ label = "factory";
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom: eeprom@0 {
+ reg = <0x0 0x1000>;
+ };
+
+ macaddr: macaddr@4 {
+ reg = <0x4 0x6>;
+ };
+ };
+ };
+
+ partition@380000 {
+ reg = <0x380000 0x200000>;
+ label = "fip";
+ };
+
+ partition@580000 {
+ reg = <0x580000 0x4000000>;
+ label = "ubi";
+ };
+ };
+ };
+};
+
+&trng {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&wifi {
+ nvmem-cells = <&eeprom>;
+ nvmem-cell-names = "eeprom";
+ status = "okay";
+};
--
2.35.3
next prev parent reply other threads:[~2023-12-04 20:09 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-04 20:09 [PATCH V2 1/3] dt-bindings: vendor-prefixes: add acelink Rafał Miłecki
2023-12-04 20:09 ` [PATCH V2 2/3] dt-bindings: arm64: dts: mediatek: Add Acelink EW-7886CAX access point Rafał Miłecki
2023-12-05 13:15 ` AngeloGioacchino Del Regno
2023-12-04 20:09 ` Rafał Miłecki [this message]
2023-12-05 13:16 ` [PATCH V2 3/3] arm64: dts: mediatek: Add Acelink EW-7886CAX AngeloGioacchino Del Regno
2023-12-05 13:17 ` AngeloGioacchino Del Regno
2023-12-05 21:04 ` kernel test robot
2023-12-05 21:44 ` Rafał Miłecki
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