From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E9FB58101; Tue, 5 Dec 2023 15:01:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bu7k/46z" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 73FEEC433C7; Tue, 5 Dec 2023 15:01:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701788477; bh=kYRwODFbLu0AAQRqnx93sSXNYsrdMTvxC35fEtnlADI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=bu7k/46zMNkwk9yLv5gCLuP2gbZ1VDWR/jKO8pjqj2ofoMUg7WHpPW8NJG3hIYjMS UVKx47KoiAdKzX1PvRK1IfLnS0vXpS0IwzKtvADJjcnIP/2wquEyaZ72DL8Gdm2E6J N1iDYq5i8BwFTk4G1SjJirzk49ku6ccbHuOKJohmKUZMXdiuOidWsMaI++2Xhxn080 RNxBmWf/b/JfP2nG9g69+HFA+a1tcsHUvcL5GTeq7IENNmqMY9/3Bt6athRgjPVoiB f8jo8ucsEuY87yrvbq+ATLzfjos+qZD4Ly2ygaNH4ATshdnpU2lU1US5mcWE359xa9 08Vl9Vfd/Bggg== Date: Tue, 5 Dec 2023 20:31:01 +0530 From: Manivannan Sadhasivam To: Luca Weiss Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nitin Rawat Subject: Re: [PATCH v6 2/3] arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 soc Message-ID: <20231205150101.GB3208@thinkpad> References: <20231205-sc7280-ufs-v6-0-ad6ca7796de7@fairphone.com> <20231205-sc7280-ufs-v6-2-ad6ca7796de7@fairphone.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20231205-sc7280-ufs-v6-2-ad6ca7796de7@fairphone.com> On Tue, Dec 05, 2023 at 03:38:55PM +0100, Luca Weiss wrote: > From: Nitin Rawat > > Add UFS host controller and PHY nodes for sc7280 soc. > > Signed-off-by: Nitin Rawat > Reviewed-by: Konrad Dybcio > Tested-by: Konrad Dybcio # QCM6490 FP5 > [luca: various cleanups and additions as written in the cover letter] > Signed-off-by: Luca Weiss Acked-by: Manivannan Sadhasivam - Mani > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 74 +++++++++++++++++++++++++++++++++++- > 1 file changed, 73 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 04bf85b0399a..dcb6c2004f87 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -906,7 +907,7 @@ gcc: clock-controller@100000 { > clocks = <&rpmhcc RPMH_CXO_CLK>, > <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, > <0>, <&pcie1_phy>, > - <0>, <0>, <0>, > + <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, > <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; > clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", > "pcie_0_pipe_clk", "pcie_1_pipe_clk", > @@ -2238,6 +2239,77 @@ pcie1_phy: phy@1c0e000 { > status = "disabled"; > }; > > + ufs_mem_hc: ufs@1d84000 { > + compatible = "qcom,sc7280-ufshc", "qcom,ufshc", > + "jedec,ufs-2.0"; > + reg = <0x0 0x01d84000 0x0 0x3000>; > + interrupts = ; > + phys = <&ufs_mem_phy>; > + phy-names = "ufsphy"; > + lanes-per-direction = <2>; > + #reset-cells = <1>; > + resets = <&gcc GCC_UFS_PHY_BCR>; > + reset-names = "rst"; > + > + power-domains = <&gcc GCC_UFS_PHY_GDSC>; > + required-opps = <&rpmhpd_opp_nom>; > + > + iommus = <&apps_smmu 0x80 0x0>; > + dma-coherent; > + > + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "ufs-ddr", "cpu-ufs"; > + > + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > + <&gcc GCC_UFS_PHY_AHB_CLK>, > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; > + clock-names = "core_clk", > + "bus_aggr_clk", > + "iface_clk", > + "core_clk_unipro", > + "ref_clk", > + "tx_lane0_sync_clk", > + "rx_lane0_sync_clk", > + "rx_lane1_sync_clk"; > + freq-table-hz = > + <75000000 300000000>, > + <0 0>, > + <0 0>, > + <75000000 300000000>, > + <0 0>, > + <0 0>, > + <0 0>, > + <0 0>; > + status = "disabled"; > + }; > + > + ufs_mem_phy: phy@1d87000 { > + compatible = "qcom,sc7280-qmp-ufs-phy"; > + reg = <0x0 0x01d87000 0x0 0xe00>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, > + <&gcc GCC_UFS_1_CLKREF_EN>; > + clock-names = "ref", "ref_aux", "qref"; > + > + power-domains = <&rpmhpd SC7280_MX>; > + > + resets = <&ufs_mem_hc 0>; > + reset-names = "ufsphy"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > ipa: ipa@1e40000 { > compatible = "qcom,sc7280-ipa"; > > > -- > 2.43.0 > -- மணிவண்ணன் சதாசிவம்