From: Conor Dooley <conor@kernel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Inochi Amaoto <inochiama@outlook.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Chao Wei <chao.wei@sophgo.com>,
Chen Wang <unicorn_wang@outlook.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Jisheng Zhang <jszhang@kernel.org>,
Liu Gui <kenneth.liu@sophgo.com>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
qiujingbao.dlmu@gmail.com, dlan@gentoo.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 3/4] riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC
Date: Thu, 7 Dec 2023 17:31:33 +0000 [thread overview]
Message-ID: <20231207-doze-spinster-0bfad3b1441a@spud> (raw)
In-Reply-To: <375bb6e4-18dc-4f54-9a06-6f9f2ba0a0ec@linaro.org>
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On Thu, Dec 07, 2023 at 01:52:16PM +0100, Krzysztof Kozlowski wrote:
> On 07/12/2023 10:42, Inochi Amaoto wrote:
> >>> +&clk {
> >>> + compatible = "sophgo,cv1810-clk";
> >>> +};
> >>> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> >>> index 2d6f4a4b1e58..6ea1b2784db9 100644
> >>> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> >>> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> >>> @@ -53,6 +53,12 @@ soc {
> >>> dma-noncoherent;
> >>> ranges;
> >>>
> >>> + clk: clock-controller@3002000 {
> >>> + reg = <0x03002000 0x1000>;
> >>> + clocks = <&osc>;
> >>> + #clock-cells = <1>;
> >>
> >> I don't find such layout readable and maintainable. I did some parts
> >> like this long, long time ago for one of my SoCs (Exynos54xx), but I
> >> find it over time unmaintainable approach. I strongly suggest to have
> >> compatible and other properties in one place, so cv1800 and cv1812, even
> >> if it duplicates the code.
> >>
> >
> > Hi Krzysztof:
> >
> > Thanks for your advice, but I have a question about this: when I should
> > use the DT override? The memory mapping of the CV1800 and CV1810 are
> > almost the same (the CV1810 have more peripheral and the future SG200X
> > have the same layout). IIRC, this is why conor suggested using DT override
> > to make modification easier. But duplicating node seems to break thiS, so
> > I's pretty confused.
>
> Go with whatever your subarchitecture and architecture maintainers
> prefer, I just shared my opinion that I find such code difficult to read
> and maintain.
>
> Extending node with supplies, pinctrl or even clocks would be readable.
> But the compatible: no. The same applies when you need to delete
> property or subnode: not readable/maintainable IMHO.
There are apparently 3 or 4 of these SoCs that are basically identical,
which is why the approach was taken. I do agree that it looks somewhat
messy because I was looking for device-specific compatibles for these
SoCs.
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next prev parent reply other threads:[~2023-12-07 17:31 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-07 8:36 [PATCH v3 0/4] riscv: sophgo: add clock support for Sophgo CV1800 SoCs Inochi Amaoto
2023-12-07 8:37 ` [PATCH v3 1/4] dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC Inochi Amaoto
2023-12-07 9:17 ` Krzysztof Kozlowski
2023-12-07 8:37 ` [PATCH v3 2/4] clk: sophgo: Add CV1800 series clock controller driver Inochi Amaoto
2023-12-11 17:48 ` Rob Herring
2023-12-18 4:06 ` Inochi Amaoto
2023-12-07 8:37 ` [PATCH v3 3/4] riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC Inochi Amaoto
2023-12-07 9:19 ` Krzysztof Kozlowski
2023-12-07 9:42 ` Inochi Amaoto
2023-12-07 12:52 ` Krzysztof Kozlowski
2023-12-07 17:31 ` Conor Dooley [this message]
2023-12-08 1:13 ` Inochi Amaoto
2023-12-08 15:02 ` Conor Dooley
2023-12-09 2:40 ` Inochi Amaoto
2023-12-07 8:37 ` [PATCH v3 4/4] riscv: dts: sophgo: add uart clock " Inochi Amaoto
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