From: Rob Herring <robh@kernel.org>
To: Luo Jie <quic_luoj@quicinc.com>
Cc: agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, davem@davemloft.net,
edumazet@google.com, kuba@kernel.org, pabeni@redhat.com,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk,
robert.marko@sartura.hr, linux-arm-msm@vger.kernel.org,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, quic_srichara@quicinc.com
Subject: Re: [PATCH v2 5/5] dt-bindings: net: ipq4019-mdio: Document ipq5332 platform
Date: Tue, 12 Dec 2023 14:06:41 -0600 [thread overview]
Message-ID: <20231212200641.GA2331615-robh@kernel.org> (raw)
In-Reply-To: <20231212115151.20016-6-quic_luoj@quicinc.com>
On Tue, Dec 12, 2023 at 07:51:50PM +0800, Luo Jie wrote:
> Update the yaml file for the new DTS properties.
>
> 1. cmn-reference-clock for the CMN PLL source clock select.
> 2. clock-frequency for MDIO clock frequency config.
> 3. add uniphy AHB & SYS GCC clocks.
> 4. add reset-gpios for MDIO bus level reset.
>
> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
> ---
> .../bindings/net/qcom,ipq4019-mdio.yaml | 157 +++++++++++++++++-
> 1 file changed, 153 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
> index 3407e909e8a7..9546a6ad7841 100644
> --- a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
> +++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
> @@ -20,6 +20,8 @@ properties:
> - enum:
> - qcom,ipq6018-mdio
> - qcom,ipq8074-mdio
> + - qcom,ipq9574-mdio
> + - qcom,ipq5332-mdio
> - const: qcom,ipq4019-mdio
A driver can function without knowing about all these new registers and
clocks? If not, then it can't be compatible with "qcom,ipq4019-mdio".
>
> "#address-cells":
> @@ -30,19 +32,71 @@ properties:
>
> reg:
> minItems: 1
> - maxItems: 2
> + maxItems: 5
> description:
> - the first Address and length of the register set for the MDIO controller.
> - the second Address and length of the register for ethernet LDO, this second
> - address range is only required by the platform IPQ50xx.
> + the first Address and length of the register set for the MDIO controller,
> + the optional second, third and fourth address and length of the register
> + for ethernet LDO, these three address range are required by the platform
> + IPQ50xx/IPQ5332/IPQ9574, the last address and length is for the CMN clock
> + to select the reference clock.
> +
> + reg-names:
> + minItems: 1
> + maxItems: 5
>
> clocks:
> + minItems: 1
> items:
> - description: MDIO clock source frequency fixed to 100MHZ
> + - description: UNIPHY0 AHB clock source frequency fixed to 100MHZ
> + - description: UNIPHY1 AHB clock source frequency fixed to 100MHZ
> + - description: UNIPHY0 SYS clock source frequency fixed to 24MHZ
> + - description: UNIPHY1 SYS clock source frequency fixed to 24MHZ
These are all clock inputs to this h/w block and not some other clocks
you want to manage?
>
> clock-names:
> + minItems: 1
> items:
> - const: gcc_mdio_ahb_clk
> + - const: gcc_uniphy0_ahb_clk
> + - const: gcc_uniphy1_ahb_clk
> + - const: gcc_uniphy0_sys_clk
> + - const: gcc_uniphy1_sys_clk
"gcc" is presumably the name of the clock controller in QCom chips.
Well, the clock source should not be part of the binding. The names
should be local for what they are for. So drop 'gcc_'. And '_clk' is
also redundant, so drop it too. Unfortunately you are stuck with the
name of the 1st entry.
> +
> + cmn-reference-clock:
> + oneOf:
> + - items:
> + - enum:
> + - 0 # CMN PLL reference internal 48MHZ
> + - 1 # CMN PLL reference external 25MHZ
> + - 2 # CMN PLL reference external 31250KHZ
> + - 3 # CMN PLL reference external 40MHZ
> + - 4 # CMN PLL reference external 48MHZ
> + - 5 # CMN PLL reference external 50MHZ
> + - 6 # CMN PLL reference internal 96MHZ
> +
> + clock-frequency:
> + oneOf:
> + - items:
> + - enum:
> + - 12500000
> + - 6250000
> + - 3125000
> + - 1562500
> + - 781250
> + - 390625
> + description:
> + The MDIO bus clock that must be output by the MDIO bus hardware,
> + only the listed frequecies above can be configured, other frequency
> + will cause malfunction. If absent, the default hardware value is used.
> +
> + reset-gpios:
> + maxItems: 1
> +
> + reset-assert-us:
> + maxItems: 1
> +
> + reset-deassert-us:
> + maxItems: 1
>
> required:
> - compatible
> @@ -61,6 +115,8 @@ allOf:
> - qcom,ipq5018-mdio
> - qcom,ipq6018-mdio
> - qcom,ipq8074-mdio
> + - qcom,ipq5332-mdio
> + - qcom,ipq9574-mdio
> then:
> required:
> - clocks
> @@ -70,6 +126,40 @@ allOf:
> clocks: false
> clock-names: false
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq5332-mdio
> + then:
> + properties:
> + clocks:
> + minItems: 5
> + maxItems: 5
> + reg-names:
> + items:
> + - const: mdio
> + - const: eth_ldo1
> + - const: eth_ldo2
> + - const: cmn_blk
Perhaps cmn_blk should come 2nd, so all the variants have the same entry
indices. Then you can move this to the top level and just say 'minItems:
4' here.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq9574-mdio
> + then:
> + properties:
> + reg-names:
> + items:
> + - const: mdio
> + - const: eth_ldo1
> + - const: eth_ldo2
> + - const: eth_ldo3
> + - const: cmn_blk
And 'minItems: 5' here.
The ipq9574 adds the CMN block, but none of the clocks? Weird.
Rob
next prev parent reply other threads:[~2023-12-12 20:06 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-12 11:51 [PATCH v2 0/5] support ipq5332 platform Luo Jie
2023-12-12 11:51 ` [PATCH v2 1/5] net: mdio: ipq4019: move eth_ldo_rdy before MDIO bus register Luo Jie
2023-12-12 12:50 ` Maxime Chevallier
2023-12-12 19:11 ` Russell King (Oracle)
2023-12-13 10:07 ` Maxime Chevallier
2023-12-12 11:51 ` [PATCH v2 2/5] net: mdio: ipq4019: enable the SoC uniphy clocks for ipq5332 platform Luo Jie
2023-12-12 12:46 ` Maxime Chevallier
2023-12-13 8:05 ` Jie Luo
2023-12-12 11:51 ` [PATCH v2 3/5] net: mdio: ipq4019: configure CMN PLL clock for ipq5332 Luo Jie
2023-12-12 12:54 ` Maxime Chevallier
2023-12-12 19:12 ` Russell King (Oracle)
2023-12-13 8:09 ` Jie Luo
2023-12-13 10:08 ` Maxime Chevallier
2023-12-12 11:51 ` [PATCH v2 4/5] net: mdio: ipq4019: support MDIO clock frequency divider Luo Jie
2023-12-12 11:51 ` [PATCH v2 5/5] dt-bindings: net: ipq4019-mdio: Document ipq5332 platform Luo Jie
2023-12-12 13:24 ` Rob Herring
2023-12-12 16:06 ` Conor Dooley
2023-12-13 8:26 ` Jie Luo
2023-12-14 17:12 ` Conor Dooley
2023-12-15 6:46 ` Jie Luo
2023-12-15 7:29 ` Krzysztof Kozlowski
2023-12-15 9:49 ` Jie Luo
2023-12-15 10:19 ` Krzysztof Kozlowski
2023-12-15 10:33 ` Jie Luo
2023-12-15 10:37 ` Krzysztof Kozlowski
2023-12-15 10:40 ` Jie Luo
2023-12-15 10:53 ` Krzysztof Kozlowski
2023-12-15 11:42 ` Jie Luo
2023-12-15 12:19 ` Krzysztof Kozlowski
2023-12-15 12:40 ` Jie Luo
2023-12-15 13:39 ` Andrew Lunn
2023-12-16 13:31 ` Jie Luo
2023-12-15 13:41 ` Conor Dooley
2023-12-16 13:16 ` Jie Luo
2023-12-16 14:16 ` Conor Dooley
2023-12-16 15:37 ` Jie Luo
2023-12-19 15:47 ` Conor Dooley
2023-12-20 10:07 ` Jie Luo
2023-12-20 7:28 ` Krzysztof Kozlowski
2023-12-20 10:11 ` Jie Luo
2023-12-15 10:42 ` Conor Dooley
2023-12-15 11:42 ` Jie Luo
2023-12-12 20:06 ` Rob Herring [this message]
2023-12-13 8:42 ` Jie Luo
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