[PATCH 02/10] clk: qcom: ipq5332: Add separate clocks for PCIe and USB for Combo PHY

[Praveenkumar I <quic_ipkumar@quicinc.com>]

Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the
interface (PCIe/USB) can use this combo PHY and the PHY drivers are
different for PCIe and USB. Hence separate the PCIe and USB pipe clock
source from DT, and individual driver node can be used as a clock source
separately in the gcc. Add separate enum for PCIe and USB pipe clock and
change the parent in corresponding structures.

Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
---
 drivers/clk/qcom/gcc-ipq5332.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index f98591148a97..aa0f616c3b1b 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -25,7 +25,8 @@ enum {
 	DT_SLEEP_CLK,
 	DT_PCIE_2LANE_PHY_PIPE_CLK,
 	DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
-	DT_USB_PCIE_WRAPPER_PIPE_CLK,
+	DT_PCIE_WRAPPER_PIPE_CLK,
+	DT_USB_WRAPPER_PIPE_CLK,
 };
 
 enum {
@@ -728,7 +729,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = {
 		.hw.init = &(struct clk_init_data) {
 			.name = "gcc_pcie3x1_0_pipe_clk_src",
 			.parent_data = &(const struct clk_parent_data) {
-				.index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
+				.index = DT_PCIE_WRAPPER_PIPE_CLK,
 			},
 			.num_parents = 1,
 			.ops = &clk_regmap_phy_mux_ops,
@@ -1072,7 +1073,7 @@ static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
 		.hw.init = &(struct clk_init_data) {
 			.name = "gcc_usb0_pipe_clk_src",
 			.parent_data = &(const struct clk_parent_data) {
-				.index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
+				.index = DT_USB_WRAPPER_PIPE_CLK,
 			},
 			.num_parents = 1,
 			.ops = &clk_regmap_phy_mux_ops,
-- 
2.34.1