* [PATCH 1/2] arm64: dts: imx8qm: Align edma3 power-domains resources indentation
@ 2023-12-14 19:46 Frank Li
2023-12-14 19:46 ` [PATCH 2/2] arm64: dts: imx8qm: Correct edma3 power-domains and interrupt numbers Frank Li
2024-02-01 10:04 ` [PATCH 1/2] arm64: dts: imx8qm: Align edma3 power-domains resources indentation Shawn Guo
0 siblings, 2 replies; 3+ messages in thread
From: Frank Li @ 2023-12-14 19:46 UTC (permalink / raw)
To: shawnguo, xiaolei.wang
Cc: Frank.li, conor+dt, devicetree, festevam, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
marcel.ziswiler, qiangqing.zhang, robh+dt, s.hauer
<&pd IMX_SC_R_DMA_1_CH*> is now properly aligned with the previous line
for improved code readability.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
index 69cb8676732ea..453fabfd17b81 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
@@ -98,13 +98,13 @@ &edma2 {
&edma3 {
power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
- <&pd IMX_SC_R_DMA_1_CH1>,
- <&pd IMX_SC_R_DMA_1_CH2>,
- <&pd IMX_SC_R_DMA_1_CH3>,
- <&pd IMX_SC_R_DMA_1_CH4>,
- <&pd IMX_SC_R_DMA_1_CH5>,
- <&pd IMX_SC_R_DMA_1_CH6>,
- <&pd IMX_SC_R_DMA_1_CH7>;
+ <&pd IMX_SC_R_DMA_1_CH1>,
+ <&pd IMX_SC_R_DMA_1_CH2>,
+ <&pd IMX_SC_R_DMA_1_CH3>,
+ <&pd IMX_SC_R_DMA_1_CH4>,
+ <&pd IMX_SC_R_DMA_1_CH5>,
+ <&pd IMX_SC_R_DMA_1_CH6>,
+ <&pd IMX_SC_R_DMA_1_CH7>;
};
&flexcan1 {
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH 2/2] arm64: dts: imx8qm: Correct edma3 power-domains and interrupt numbers
2023-12-14 19:46 [PATCH 1/2] arm64: dts: imx8qm: Align edma3 power-domains resources indentation Frank Li
@ 2023-12-14 19:46 ` Frank Li
2024-02-01 10:04 ` [PATCH 1/2] arm64: dts: imx8qm: Align edma3 power-domains resources indentation Shawn Guo
1 sibling, 0 replies; 3+ messages in thread
From: Frank Li @ 2023-12-14 19:46 UTC (permalink / raw)
To: shawnguo, xiaolei.wang
Cc: Frank.li, conor+dt, devicetree, festevam, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
marcel.ziswiler, qiangqing.zhang, robh+dt, s.hauer
It is eDMA1 at QM, which have the same register with eDMA3 at qxp.
The below commit fix panic problem.
commit b37e75bddc35 ("arm64: dts: imx8qm: Add imx8qm's own pm to avoid panic during startup")
This fixes the IRQ and DMA channel numbers. While QM eDMA1 technically has
32 channels, only 10 channels are likely used for I2C. The exact IRQ
numbers for the remaining channels were unclear in the reference manual.
Fixes: e4d7a330fb7a ("arm64: dts: imx8: add edma[0..3]")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
.../arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
index 453fabfd17b81..cafc1383115ab 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
@@ -96,7 +96,20 @@ &edma2 {
status = "okay";
};
+/* It is eDMA1 in 8QM RM, but 8QXP it is eDMA3 */
&edma3 {
+ reg = <0x5a9f0000 0x210000>;
+ dma-channels = <10>;
+ interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
<&pd IMX_SC_R_DMA_1_CH1>,
<&pd IMX_SC_R_DMA_1_CH2>,
@@ -104,7 +117,9 @@ &edma3 {
<&pd IMX_SC_R_DMA_1_CH4>,
<&pd IMX_SC_R_DMA_1_CH5>,
<&pd IMX_SC_R_DMA_1_CH6>,
- <&pd IMX_SC_R_DMA_1_CH7>;
+ <&pd IMX_SC_R_DMA_1_CH7>,
+ <&pd IMX_SC_R_DMA_1_CH8>,
+ <&pd IMX_SC_R_DMA_1_CH9>;
};
&flexcan1 {
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH 1/2] arm64: dts: imx8qm: Align edma3 power-domains resources indentation
2023-12-14 19:46 [PATCH 1/2] arm64: dts: imx8qm: Align edma3 power-domains resources indentation Frank Li
2023-12-14 19:46 ` [PATCH 2/2] arm64: dts: imx8qm: Correct edma3 power-domains and interrupt numbers Frank Li
@ 2024-02-01 10:04 ` Shawn Guo
1 sibling, 0 replies; 3+ messages in thread
From: Shawn Guo @ 2024-02-01 10:04 UTC (permalink / raw)
To: Frank Li
Cc: shawnguo, xiaolei.wang, conor+dt, devicetree, festevam, imx,
kernel, krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx,
linux-kernel, marcel.ziswiler, qiangqing.zhang, robh+dt, s.hauer
On Thu, Dec 14, 2023 at 02:46:54PM -0500, Frank Li wrote:
> <&pd IMX_SC_R_DMA_1_CH*> is now properly aligned with the previous line
> for improved code readability.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
Applied both, thanks!
^ permalink raw reply [flat|nested] 3+ messages in thread
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