From: "Krzysztof Wilczyński" <kw@linux.com>
To: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, bhelgaas@google.com,
lpieralisi@kernel.org, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, colnor+dt@kernel.org,
michal.simek@amd.com, bharat.kumar.gogada@amd.com
Subject: Re: [PATCH v5 RESEND 0/4] increase ecam size value to discover 256 buses during
Date: Sun, 17 Dec 2023 06:31:21 +0900 [thread overview]
Message-ID: <20231216213121.GB3302836@rocinante> (raw)
In-Reply-To: <20231016051102.1180432-1-thippeswamy.havalige@amd.com>
Hello,
> Current driver is supports up to 16 buses. The following code fixes
> to support up to 256 buses.
>
> update "NWL_ECAM_VALUE_DEFAULT " to 16 can access up to 256MB ECAM
> region to detect 256 buses.
>
> Update ecam size to 256MB in device tree binding example.
>
> Remove unwanted code.
Applied to controller/xilinx-ecam, thank you!
[01/04] PCI: xilinx-nwl: Remove redundant code that sets Type 1 header fields
https://git.kernel.org/pci/pci/c/a2492ff1fcb9
[02/04] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in the DT example
https://git.kernel.org/pci/pci/c/22f38a244273
[03/04] PCI: xilinx-nwl: Rename the NWL_ECAM_VALUE_DEFAULT macro
https://git.kernel.org/pci/pci/c/177692115f6f
[04/04] PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses
https://git.kernel.org/pci/pci/c/2fccd11518f1
Krzysztof
prev parent reply other threads:[~2023-12-16 21:31 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-16 5:10 [PATCH v5 RESEND 0/4] increase ecam size value to discover 256 buses during Thippeswamy Havalige
2023-10-16 5:10 ` [PATCH v5 RESEND 1/4] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers Thippeswamy Havalige
2023-10-16 5:11 ` [PATCH v5 RESEND 2/4] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example Thippeswamy Havalige
2023-10-16 5:11 ` [PATCH v5 RESEND 3/4] PCI: xilinx-nwl: Rename ECAM size default macro Thippeswamy Havalige
2023-10-16 5:11 ` [PATCH v5 RESEND 4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Thippeswamy Havalige
2023-10-20 10:35 ` [PATCH v5 RESEND 0/4] increase ecam size value to discover 256 buses during Havalige, Thippeswamy
2023-10-23 17:26 ` Bjorn Helgaas
2023-10-23 17:36 ` Havalige, Thippeswamy
2023-12-16 21:31 ` Krzysztof Wilczyński [this message]
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