From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B6A6F1FA3; Mon, 18 Dec 2023 01:09:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BA0F01FB; Sun, 17 Dec 2023 17:10:24 -0800 (PST) Received: from minigeek.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C6A413F738; Sun, 17 Dec 2023 17:09:36 -0800 (PST) Date: Mon, 18 Dec 2023 01:09:26 +0000 From: Andre Przywara To: Maksim Kiselev Cc: Vasily Khoruzhick , Yangtao Li , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Marc Kleine-Budde , John Watts , Cristian Ciocaltea , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v6 3/3] riscv: dts: allwinner: d1: Add thermal sensor Message-ID: <20231218010926.10e15c57@minigeek.lan> In-Reply-To: <20231217210629.131486-4-bigunclemax@gmail.com> References: <20231217210629.131486-1-bigunclemax@gmail.com> <20231217210629.131486-4-bigunclemax@gmail.com> Organization: Arm Ltd. X-Mailer: Claws Mail 4.2.0 (GTK 3.24.31; x86_64-slackware-linux-gnu) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Mon, 18 Dec 2023 00:06:24 +0300 Maksim Kiselev wrote: Hi, > From: Maxim Kiselev > > This patch adds a thermal sensor controller node for the D1/T113s. > Also it adds a THS calibration data cell to efuse node. > > Signed-off-by: Maxim Kiselev > --- > .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > index 5a9d7f5a75b4..6f5427d9cfbf 100644 > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > @@ -166,6 +166,19 @@ gpadc: adc@2009000 { > #io-channel-cells = <1>; > }; > > + ths: thermal-sensor@2009400 { > + compatible = "allwinner,sun20i-d1-ths"; > + reg = <0x02009400 0x400>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_THS>; > + clock-names = "bus"; > + resets = <&ccu RST_BUS_THS>; > + nvmem-cells = <&ths_calibration>; > + nvmem-cell-names = "calibration"; > + status = "disabled"; Any reason this is disabled? We typically don't disable those internal devices in the SoC .dtsi, the THS is one example (check the instances in other SoCs' .dtsi files). The rest looks alright, compared to the manual, so with this line removed: Reviewed-by: Andre Przywara Cheers, Andre > + #thermal-sensor-cells = <0>; > + }; > + > dmic: dmic@2031000 { > compatible = "allwinner,sun20i-d1-dmic", > "allwinner,sun50i-h6-dmic"; > @@ -415,6 +428,10 @@ sid: efuse@3006000 { > reg = <0x3006000 0x1000>; > #address-cells = <1>; > #size-cells = <1>; > + > + ths_calibration: thermal-sensor-calibration@14 { > + reg = <0x14 0x4>; > + }; > }; > > crypto: crypto@3040000 {