From: Brandon Cheo Fusi <fusibrandon13@gmail.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Yangtao Li <tiny.windzz@gmail.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Viresh Kumar <viresh.kumar@linaro.org>,
Stephen Rothwell <sfr@canb.auug.org.au>
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org,
Brandon Cheo Fusi <fusibrandon13@gmail.com>
Subject: [RFC PATCH v2 1/3] cpufreq: sun50i: Refactor speed bin decoding
Date: Thu, 21 Dec 2023 11:10:11 +0100 [thread overview]
Message-ID: <20231221101013.67204-2-fusibrandon13@gmail.com> (raw)
In-Reply-To: <20231221101013.67204-1-fusibrandon13@gmail.com>
Make converting the speed bin value into a speed grade generic
and determined by a platform specific callback.
Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com>
---
drivers/cpufreq/sun50i-cpufreq-nvmem.c | 55 ++++++++++++++++++--------
1 file changed, 39 insertions(+), 16 deletions(-)
diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
index 32a9c88f8..fc509fc49 100644
--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
@@ -25,6 +25,38 @@
static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev;
+struct sunxi_cpufreq_data {
+ u32 (*efuse_xlate)(u32 *speedbin, size_t len);
+};
+
+static u32 sun50i_efuse_xlate(u32 *speedbin, size_t len)
+{
+ u32 efuse_value = 0;
+
+ efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK;
+
+ /*
+ * We treat unexpected efuse values as if the SoC was from
+ * the slowest bin. Expected efuse values are 1-3, slowest
+ * to fastest.
+ */
+ if (efuse_value >= 1 && efuse_value <= 3)
+ return efuse_value - 1;
+ else
+ return 0;
+}
+
+struct sunxi_cpufreq_data sun50i_cpufreq_data = {
+ .efuse_xlate = sun50i_efuse_xlate,
+};
+
+static const struct of_device_id cpu_opp_match_list[] = {
+ { .compatible = "allwinner,sun50i-h6-operating-points",
+ .data = &sun50i_cpufreq_data,
+ },
+ {}
+};
+
/**
* sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
* @versions: Set to the value parsed from efuse
@@ -36,9 +68,10 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
struct nvmem_cell *speedbin_nvmem;
struct device_node *np;
struct device *cpu_dev;
- u32 *speedbin, efuse_value;
+ const struct of_device_id *match;
+ const struct sunxi_cpufreq_data *opp_data;
+ u32 *speedbin;
size_t len;
- int ret;
cpu_dev = get_cpu_device(0);
if (!cpu_dev)
@@ -48,12 +81,12 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
if (!np)
return -ENOENT;
- ret = of_device_is_compatible(np,
- "allwinner,sun50i-h6-operating-points");
- if (!ret) {
+ match = of_match_node(cpu_opp_match_list, np);
+ if (!match) {
of_node_put(np);
return -ENOENT;
}
+ opp_data = match->data;
speedbin_nvmem = of_nvmem_cell_get(np, NULL);
of_node_put(np);
@@ -66,17 +99,7 @@ static int sun50i_cpufreq_get_efuse(u32 *versions)
if (IS_ERR(speedbin))
return PTR_ERR(speedbin);
- efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK;
-
- /*
- * We treat unexpected efuse values as if the SoC was from
- * the slowest bin. Expected efuse values are 1-3, slowest
- * to fastest.
- */
- if (efuse_value >= 1 && efuse_value <= 3)
- *versions = efuse_value - 1;
- else
- *versions = 0;
+ *versions = opp_data->efuse_xlate(speedbin, len);
kfree(speedbin);
return 0;
--
2.30.2
next prev parent reply other threads:[~2023-12-21 10:10 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-21 10:10 [RFC PATCH v2 0/3] Add support for reading D1 efuse speed bin Brandon Cheo Fusi
2023-12-21 10:10 ` Brandon Cheo Fusi [this message]
2023-12-21 10:10 ` [RFC PATCH v2 2/3] cpufreq: sun50i: Add support for D1's speed bin decoding Brandon Cheo Fusi
2023-12-21 12:49 ` Andre Przywara
2023-12-21 17:11 ` Brandon Cheo Fusi
2023-12-21 17:26 ` Andre Przywara
2023-12-21 10:10 ` [RFC PATCH v2 3/3] riscv: dts: allwinner: Fill in OPPs Brandon Cheo Fusi
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