[PATCH v6 10/16] dt-bindings: riscv: Add Andes PMU extension description

Yu Chien Peter Lin
2023-12-25T10:48:53Z

Document the ISA string for Andes Technology performance monitor
extension which provides counter overflow interrupt and mode
filtering mechanisms.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Changes v2 -> v3:
- New patch
Changes v3 -> v4:
- Include Conor's Acked-by
Changes v4 -> v5:
- Include Prabhakar's Reviewed-by
Changes v5 -> v6:
- No change
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index b5cb8ac7ac80..daef6c3b1580 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -258,6 +258,13 @@ properties:
in commit 2e5236 ("Ztso is now ratified.") of the
riscv-isa-manual.

+ - const: xandespmu
+ description:
+ The Andes Technology performance monitor extension for counter overflow
+ and privilege mode filtering. For more details, see Counter Related
+ Registers in the AX45MP datasheet.
+ https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+
- const: xtheadpmu
description:
The T-Head performance monitor extension for counter overflow, as ratified
--
2.34.1