[PATCH 3/3] riscv: dts: starfive: jh8100: Add SD/eMMC device tree nodes

[Alex Soo <yuklin.soo@starfivetech.com>]

Add SD/eMMC device tree nodes.

Signed-off-by: Alex Soo <yuklin.soo@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh8100.dtsi | 34 ++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi
index 9c8ca73fffe0..545109ca6c49 100644
--- a/arch/riscv/boot/dts/starfive/jh8100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi
@@ -484,6 +484,15 @@ syscrg_sw: syscrg_sw@12720000 {
 			#reset-cells = <1>;
 		};
 
+		sd1: mmc@12740000 {
+			compatible = "starfive,jh8100-sd6hc", "cdns,sd6hc";
+			reg = <0x0 0x12740000 0x0 0x10000>;
+			interrupts = <91>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			status = "disabled";
+		};
+
 		pinctrl_gmac: pinctrl@12770000 {
 			compatible = "starfive,jh8100-sys-pinctrl-gmac",
 				     "syscon", "simple-mfd";
@@ -509,6 +518,31 @@ uart6: serial@127e0000  {
 			status = "disabled";
 		};
 
+		emmc: mmc@1f110000 {
+			compatible = "starfive,jh8100-sd6hc", "cdns,sd6hc";
+			reg = <0x0 0x1f110000 0x0 0x10000>;
+			interrupts = <174>;
+			clock-names = "main", "sdmclk";
+			clocks = <&aoncrg AONCRG_CLK_EMMC_ICG_EN>,
+				 <&aoncrg AONCRG_CLK_EMMC_SDMCLK>;
+			resets = <&aoncrg AONCRG_RSTN_EMMC>;
+			bus-width = <8>;
+			status = "disabled";
+		};
+
+		sd0: mmc@1f120000 {
+			compatible = "starfive,jh8100-sd6hc", "cdns,sd6hc";
+			reg = <0x0 0x1f120000 0x0 0x10000>;
+			interrupts = <175>;
+			clock-names = "main", "sdmclk";
+			clocks = <&aoncrg AONCRG_CLK_SDIO0_ICG_EN>,
+				 <&aoncrg AONCRG_CLK_SDIO0_SDMCLK>;
+			resets = <&aoncrg AONCRG_RSTN_SDIO0>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			status = "disabled";
+		};
+
 		pinctrl_aon: pinctrl@1f300000 {
 			compatible = "starfive,jh8100-aon-pinctrl",
 				     "syscon", "simple-mfd";
-- 
2.25.1