From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90C385466F; Mon, 8 Jan 2024 17:31:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="un01cIWs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BB9E7C433C8; Mon, 8 Jan 2024 17:31:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1704735083; bh=TpcI3dIuWNjlKbiZdSsWqC4HAoWP9zhHwULpZ+JjExE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=un01cIWsY2l7ec12fbUWfb1qr8tZmvTjPeOHQAZJDN7e8roSZWeXC8LHNqMgPmpt/ OSJq5FkZWjL4xVuyHSbSu7PnsXNvasjfv2Fewr2IM4Kn9JwVTcO+e8Atyi9TiwW0TE 2xCNujZTg4R/G6UpksnYomw7qHgAQ+vTmtoLzh4k+sBUjltbXgHCuwUabRygiYJh63 ZgkmEgfsZIbiXJaHkMiwJxqdY1kSPBHIcaKcQb5VU33KHe7SQSHhGtUqHxXc9VX8dI V4xdKwwTFgLcd5t635lQSRPyblLOgmp1KqPriyffLCc/wFGfI/YcwXKFK+C8BhEkxH BRzEyAvcqb7XQ== Date: Mon, 8 Jan 2024 17:31:17 +0000 From: Conor Dooley To: Emil Renner Berthing Cc: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , William Qiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-pwm@vger.kernel.org, Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , Hal Feng , Paul Walmsley , Palmer Dabbelt , Albert Ou Subject: Re: [PATCH v10 3/4] riscv: dts: starfive: jh7100: Add PWM node and pins configuration Message-ID: <20240108-hubcap-stubble-ecf6ea34afb9@spud> References: <20231222094548.54103-1-william.qiu@starfivetech.com> <20231222094548.54103-4-william.qiu@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="uwSZRLPC3LWeYwWV" Content-Disposition: inline In-Reply-To: --uwSZRLPC3LWeYwWV Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Jan 05, 2024 at 05:18:45AM -0800, Emil Renner Berthing wrote: > Uwe Kleine-K=F6nig wrote: > > Hello Emil, > > > > On Sun, Dec 24, 2023 at 02:49:34AM -0800, Emil Renner Berthing wrote: > > > William Qiu wrote: > > > > Add OpenCores PWM controller node and add PWM pins configuration > > > > on VisionFive 1 board. > > > > > > > > Signed-off-by: William Qiu > > > > > > Sorry, I thought I already sent my review. This looks good. > > > > > > Reviewed-by: Emil Renner Berthing > > > > Is this also an implicit Ack to take this patch via the pwm tree once > > the earlier patches are ready? Or do you want to take it via your tree? > > (Maybe already now together with the binding? If so, you can assume my > > Reviewed-by to be an implicit Ack for that.) >=20 > Yes, sorry. This is also meant to be an Ack from me. >=20 > I imagined the dt patches would go through Conor's riscv-dt-for-next bran= ch, > but the pwm tree is certainly also fine by. idk, I prefer things to go as MAINTAINERS indicates, in case something is determined to be wrong in the cycle where the patch is in the "wrong" tree. I suppose I could take the binding though, since I am CCed on every binding patch under the sun... I'd rather an explicit ack in that case though. Cheers, Conor. --uwSZRLPC3LWeYwWV Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZZwxZQAKCRB4tDGHoIJi 0nUqAP9yJe3WrgYMWXpHjBz60+ar3t/qeJkOfk0Jf5wV3nSGKQEA/+BcCFymlJ3W 7iVCVwtlZAqIdUtOXuLEG5keZjo0kwI= =7uiV -----END PGP SIGNATURE----- --uwSZRLPC3LWeYwWV--