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[46.59.36.113]) by smtp.gmail.com with ESMTPSA id d8-20020a193848000000b0050e7d58e58csm659305lfj.174.2024.01.10.04.13.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 04:13:19 -0800 (PST) Date: Wed, 10 Jan 2024 13:13:18 +0100 From: Niklas =?utf-8?Q?S=C3=B6derlund?= To: Geert Uytterhoeven Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Magnus Damm , Catalin Marinas , Will Deacon , Ulf Hansson , Cong Dang , Duy Nguyen , Hai Pham , Linh Phung , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org Subject: Re: [PATCH 07/15] clk: renesas: rcar-gen4: Add support for FRQCRC1 Message-ID: <20240110121318.GG1625657@ragnatech.se> References: Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Hi Geert, Thanks for your work. On 2024-01-08 16:33:46 +0100, Geert Uytterhoeven wrote: > R-Car V4H and V4M have a second Frequency Control Register C. > Add support for this by treating bit field offsets beyond 31 as > referring to the second register. > > Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund > --- > Tested by enabling CLOCK_ALLOW_WRITE_DEBUGFS and checking the impact of > CPU core clk rate on CPU core speed on R-Car V4M. > --- > drivers/clk/renesas/rcar-gen4-cpg.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c > index c68d8b987054131b..a2bbdad021ed8e95 100644 > --- a/drivers/clk/renesas/rcar-gen4-cpg.c > +++ b/drivers/clk/renesas/rcar-gen4-cpg.c > @@ -179,7 +179,8 @@ static struct clk * __init cpg_pll_clk_register(const char *name, > */ > #define CPG_FRQCRB 0x00000804 > #define CPG_FRQCRB_KICK BIT(31) > -#define CPG_FRQCRC 0x00000808 > +#define CPG_FRQCRC0 0x00000808 > +#define CPG_FRQCRC1 0x000008e0 > > struct cpg_z_clk { > struct clk_hw hw; > @@ -304,7 +305,12 @@ static struct clk * __init cpg_z_clk_register(const char *name, > init.parent_names = &parent_name; > init.num_parents = 1; > > - zclk->reg = reg + CPG_FRQCRC; > + if (offset < 32) { > + zclk->reg = reg + CPG_FRQCRC0; > + } else { > + zclk->reg = reg + CPG_FRQCRC1; > + offset -= 32; > + } > zclk->kick_reg = reg + CPG_FRQCRB; > zclk->hw.init = &init; > zclk->mask = GENMASK(offset + 4, offset); > -- > 2.34.1 > > -- Kind Regards, Niklas Söderlund