From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E9A853806 for ; Thu, 11 Jan 2024 17:16:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="G96cQSSH" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-40e60e13581so7964405e9.1 for ; Thu, 11 Jan 2024 09:16:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704993361; x=1705598161; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mfriAxDaivGVMjnHfnRqJc4SkjUzQn+MLu6xDC6kMZU=; b=G96cQSSHLA1CQHDzFnFxromZI+Sy6rTx2gXG80zVyKp3ScvuEVK9dTolCT5QypONLq XuQY9ge/9frITOFChkrnvb1BJhbY2U4LNgPvT1G9rD9qgLX99VVj1gkQTD+4GRx0nMwY hIzjpwa6XcEacVAKqDQhAvIY7gJJWttygt2n4Whqu6EsvBUaPtJJtAIhrvORxCu5kANr NhLzQ+Usb4Nu07cN8KMLdIaZirRZkAJ2OIK7hhqyzv1EBu8/frIC379oLosugrkYG/xb tUqLYc2BBg83AtaPuQ41ajhWh/vLWbgIugRAyNKSI4F8zKq/gTXV3BgPl6PVw9Vo4+wi s2Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704993361; x=1705598161; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mfriAxDaivGVMjnHfnRqJc4SkjUzQn+MLu6xDC6kMZU=; b=mdiSLMGqBqojZ+WAbBP4YIhY1UQTJiWasL5U0JsM8Y/kkoL0bnrV0qW38TUaJxBU8X ZsfPOpN925nGrjDyrITZQe9KkLzlaem2Wdu6IcZI2rljcjMMIsDu9dDZb2nEZFBPyHef S0He4LIHLxmmD3sLL+GCpegXmgocK8oybZsnni3uW48cWqdBCZI0PERrA/DDVEOqQ1iN 5fhUwU+Kuf+iM/NoMYNmZnUcYoB1VgJy860TKOCPyUgSuM4MkhcVwqpFqTVYLi8VcW4Y 6mGOKx2CiNYfrDOn34qE29hZjzx6Rcp6TeidCOkMr8YMVHpOI3DjELixaCk7iXsPkMxH zpSg== X-Gm-Message-State: AOJu0Yx34jSlRlZIe/pwDZaco9GrftOXaZkUvFt5chvyHzwqi1nlByEe UpTTjxIQ/2tIAaepZmNiOlMruAJcPEy2VQ== X-Google-Smtp-Source: AGHT+IFTAJjuODtinWf1j4rHE1pgTSYKJXdkWpjS64X4n3za2zDyPghtkwTmZko7PfwqInKZagaYcw== X-Received: by 2002:a05:600c:a41:b0:40e:511d:8dfe with SMTP id c1-20020a05600c0a4100b0040e511d8dfemr55096wmq.151.1704993360868; Thu, 11 Jan 2024 09:16:00 -0800 (PST) Received: from [127.0.1.1] ([37.228.218.3]) by smtp.gmail.com with ESMTPSA id fc19-20020a05600c525300b0040d839e7bb3sm6610653wmb.19.2024.01.11.09.15.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 09:16:00 -0800 (PST) From: Bryan O'Donoghue Date: Thu, 11 Jan 2024 17:15:56 +0000 Subject: [PATCH v4 3/4] arm64: dts: qcom: sc8280xp: camss: Add CCI definitions Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240111-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v4-3-cdd5c57ff1dc@linaro.org> References: <20240111-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v4-0-cdd5c57ff1dc@linaro.org> In-Reply-To: <20240111-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v4-0-cdd5c57ff1dc@linaro.org> To: Robert Foss , Todor Tomov , Bjorn Andersson , Konrad Dybcio , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.13-dev-4e032 sc8280xp has four Camera Control Interface (CCI) blocks which pinout to two I2C master controllers for each CCI. The CCI I2C pins are not muxed so we define them in the dtsi. Reviewed-by: Konrad Dybcio Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 307 +++++++++++++++++++++++++++++++++ 1 file changed, 307 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index febf28356ff8..1949b4fa04e9 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3451,6 +3451,169 @@ usb_1_role_switch: endpoint { }; }; + cci0: cci@ac4a000 { + compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4a000 0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_0_CLK>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + power-domains = <&camcc TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci0_default>; + pinctrl-1 = <&cci0_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac4b000 { + compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4b000 0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_1_CLK>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + power-domains = <&camcc TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci1_default>; + pinctrl-1 = <&cci1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci2: cci@ac4c000 { + compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4c000 0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_2_CLK>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + power-domains = <&camcc TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci2_default>; + pinctrl-1 = <&cci2_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci2_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci3: cci@ac4d000 { + compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4d000 0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_3_CLK>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + power-domains = <&camcc TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci3_default>; + pinctrl-1 = <&cci3_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci3_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci3_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sc8280xp-camcc"; reg = <0 0x0ad00000 0 0x20000>; @@ -4076,6 +4239,150 @@ tlmm: pinctrl@f100000 { #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 230>; wakeup-parent = <&pdc>; + + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio113", "gpio114"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_i2c1_default: cci0-i2c1-default-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio115", "gpio116"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio113", "gpio114"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio115", "gpio116"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio10","gpio11"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_i2c1_default: cci1-i2c1-default-pins { + /* cci_i2c_sda3, cci_i2c_scl3 */ + pins = "gpio123","gpio124"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio10","gpio11"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { + /* cci_i2c_sda3, cci_i2c_scl3 */ + pins = "gpio123","gpio124"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci2_default: cci2-default-state { + cci2_i2c0_default: cci2-i2c0-default-pins { + /* cci_i2c_sda4, cci_i2c_scl4 */ + pins = "gpio117","gpio118"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci2_i2c1_default: cci2-i2c1-default-pins { + /* cci_i2c_sda5, cci_i2c_scl5 */ + pins = "gpio12","gpio13"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci2_sleep: cci2-sleep-state { + cci2_i2c0_sleep: cci2-i2c0-sleep-pins { + /* cci_i2c_sda4, cci_i2c_scl4 */ + pins = "gpio117","gpio118"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci2_i2c1_sleep: cci2-i2c1-sleep-pins { + /* cci_i2c_sda5, cci_i2c_scl5 */ + pins = "gpio12","gpio13"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci3_default: cci3-default-state { + cci3_i2c0_default: cci3-i2c0-default-pins { + /* cci_i2c_sda6, cci_i2c_scl6 */ + pins = "gpio145","gpio146"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci3_i2c1_default: cci3-i2c1-default-pins { + /* cci_i2c_sda7, cci_i2c_scl7 */ + pins = "gpio164","gpio165"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci3_sleep: cci3-sleep-state { + cci3_i2c0_sleep: cci3-i2c0-sleep-pins { + /* cci_i2c_sda6, cci_i2c_scl6 */ + pins = "gpio145","gpio146"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci3_i2c1_sleep: cci3-i2c1-sleep-pins { + /* cci_i2c_sda7, cci_i2c_scl7 */ + pins = "gpio164","gpio165"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; }; apps_smmu: iommu@15000000 { -- 2.42.0