* [PATCH 0/2] Add common1 register space for TI Keystone displays @ 2024-01-15 12:57 Devarsh Thakkar 2024-01-15 12:57 ` [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add support for common1 region Devarsh Thakkar 2024-01-15 12:57 ` [DO NOT MERGE PATCH 2/2] arm64: dts: ti: Add common1 register space for AM62x and AM65x SoCs Devarsh Thakkar 0 siblings, 2 replies; 13+ messages in thread From: Devarsh Thakkar @ 2024-01-15 12:57 UTC (permalink / raw) To: jyri.sarha, tomi.valkeinen, airlied, daniel, maarten.lankhorst, mripard, tzimmermann, robh+dt, krzysztof.kozlowski+dt, conor+dt, dri-devel, devicetree, linux-kernel Cc: praneeth, nm, vigneshr, a-bhatia1, j-luthra, kristo, devarsht Add common1 register space for SoC's supporting TI Keystone displays present in AM65x and AM62x SoCs. This is required to support use-cases where Linux may want to use common1 region instead of common region with the latter being controlled by another processing core. The enumeration of common1 region in device-tree bindings seem to be a miss as ideally bindings should enumerate all supported register spaces as done in Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml which also uses TI Keystone display subsystem albeit with some more features. Devarsh Thakkar (2): dt-bindings: display: ti,am65x-dss: Add support for common1 region arm64: dts: ti: Add common1 register space for AM62x and AM65x SoCs .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 7 +++++-- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++-- 3 files changed, 11 insertions(+), 6 deletions(-) -- 2.34.1 ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add support for common1 region 2024-01-15 12:57 [PATCH 0/2] Add common1 register space for TI Keystone displays Devarsh Thakkar @ 2024-01-15 12:57 ` Devarsh Thakkar 2024-01-15 16:17 ` Conor Dooley 2024-02-14 9:10 ` Tomi Valkeinen 2024-01-15 12:57 ` [DO NOT MERGE PATCH 2/2] arm64: dts: ti: Add common1 register space for AM62x and AM65x SoCs Devarsh Thakkar 1 sibling, 2 replies; 13+ messages in thread From: Devarsh Thakkar @ 2024-01-15 12:57 UTC (permalink / raw) To: jyri.sarha, tomi.valkeinen, airlied, daniel, maarten.lankhorst, mripard, tzimmermann, robh+dt, krzysztof.kozlowski+dt, conor+dt, dri-devel, devicetree, linux-kernel Cc: praneeth, nm, vigneshr, a-bhatia1, j-luthra, kristo, devarsht TI keystone display subsystem present in AM65 and other SoCs such as AM62 support two separate register spaces namely "common" and "common1" which can be used by two separate hosts to program the display controller as described in respective Technical Reference Manuals [1]. The common1 register space has similar set of configuration registers as supported in common register space except the global configuration registers which are exclusive to common region. This adds binding for "common1" register region too as supported by the hardware. [1]: AM62x TRM: https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) AM65x TRM: https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) Signed-off-by: Devarsh Thakkar <devarsht@ti.com> --- .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index b6767ef0d24d..55e3e490d0e6 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -37,6 +37,7 @@ properties: - description: OVR2 overlay manager for vp2 - description: VP1 video port 1 - description: VP2 video port 2 + - description: common1 DSS register area reg-names: items: @@ -47,6 +48,7 @@ properties: - const: ovr2 - const: vp1 - const: vp2 + - const: common1 clocks: items: @@ -147,9 +149,10 @@ examples: <0x04a07000 0x1000>, /* ovr1 */ <0x04a08000 0x1000>, /* ovr2 */ <0x04a0a000 0x1000>, /* vp1 */ - <0x04a0b000 0x1000>; /* vp2 */ + <0x04a0b000 0x1000>, /* vp2 */ + <0x04a01000 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 67 1>, -- 2.34.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add support for common1 region 2024-01-15 12:57 ` [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add support for common1 region Devarsh Thakkar @ 2024-01-15 16:17 ` Conor Dooley 2024-01-16 9:13 ` Devarsh Thakkar 2024-02-14 9:10 ` Tomi Valkeinen 1 sibling, 1 reply; 13+ messages in thread From: Conor Dooley @ 2024-01-15 16:17 UTC (permalink / raw) To: Devarsh Thakkar Cc: jyri.sarha, tomi.valkeinen, airlied, daniel, maarten.lankhorst, mripard, tzimmermann, robh+dt, krzysztof.kozlowski+dt, conor+dt, dri-devel, devicetree, linux-kernel, praneeth, nm, vigneshr, a-bhatia1, j-luthra, kristo [-- Attachment #1: Type: text/plain, Size: 2692 bytes --] On Mon, Jan 15, 2024 at 06:27:15PM +0530, Devarsh Thakkar wrote: > TI keystone display subsystem present in AM65 and other SoCs such as AM62 Do all 3 SoCs supported by this binding (am625 am62a7 am65x) have this common1 register? If not, you should limit it the platforms that do have it. Thanks, Conor. > support two separate register spaces namely "common" and "common1" which > can be used by two separate hosts to program the display controller as > described in respective Technical Reference Manuals [1]. > > The common1 register space has similar set of configuration registers as > supported in common register space except the global configuration > registers which are exclusive to common region. > > This adds binding for "common1" register region too as supported by the > hardware. > > [1]: > AM62x TRM: > https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) > > AM65x TRM: > https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) > > Signed-off-by: Devarsh Thakkar <devarsht@ti.com> > --- > .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > index b6767ef0d24d..55e3e490d0e6 100644 > --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > @@ -37,6 +37,7 @@ properties: > - description: OVR2 overlay manager for vp2 > - description: VP1 video port 1 > - description: VP2 video port 2 > + - description: common1 DSS register area > > reg-names: > items: > @@ -47,6 +48,7 @@ properties: > - const: ovr2 > - const: vp1 > - const: vp2 > + - const: common1 > > clocks: > items: > @@ -147,9 +149,10 @@ examples: > <0x04a07000 0x1000>, /* ovr1 */ > <0x04a08000 0x1000>, /* ovr2 */ > <0x04a0a000 0x1000>, /* vp1 */ > - <0x04a0b000 0x1000>; /* vp2 */ > + <0x04a0b000 0x1000>, /* vp2 */ > + <0x04a01000 0x1000>; /* common1 */ > reg-names = "common", "vidl1", "vid", > - "ovr1", "ovr2", "vp1", "vp2"; > + "ovr1", "ovr2", "vp1", "vp2", "common1"; > ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; > power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 67 1>, > -- > 2.34.1 > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add support for common1 region 2024-01-15 16:17 ` Conor Dooley @ 2024-01-16 9:13 ` Devarsh Thakkar 2024-01-16 9:36 ` Conor Dooley 0 siblings, 1 reply; 13+ messages in thread From: Devarsh Thakkar @ 2024-01-16 9:13 UTC (permalink / raw) To: Conor Dooley Cc: jyri.sarha, tomi.valkeinen, airlied, daniel, maarten.lankhorst, mripard, tzimmermann, robh+dt, krzysztof.kozlowski+dt, conor+dt, dri-devel, devicetree, linux-kernel, praneeth, nm, vigneshr, a-bhatia1, j-luthra, kristo Hi Conor, Thanks for the review. On 15/01/24 21:47, Conor Dooley wrote: > On Mon, Jan 15, 2024 at 06:27:15PM +0530, Devarsh Thakkar wrote: >> TI keystone display subsystem present in AM65 and other SoCs such as AM62 > > Do all 3 SoCs supported by this binding (am625 am62a7 am65x) have this > common1 register? If not, you should limit it the platforms that do have > it. > Yes all 3 SoCs supported by binding have common1 register space supported. AM62x TRM: https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) AM65x TRM: https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) AM62A TRM: https://www.ti.com/lit/pdf/spruj16 (Section 14.9.9.1 DSS Registers) Regards Devarsh > Thanks, > Conor. > >> support two separate register spaces namely "common" and "common1" which >> can be used by two separate hosts to program the display controller as >> described in respective Technical Reference Manuals [1]. >> >> The common1 register space has similar set of configuration registers as >> supported in common register space except the global configuration >> registers which are exclusive to common region. >> >> This adds binding for "common1" register region too as supported by the >> hardware. >> >> [1]: >> AM62x TRM: >> https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) >> >> AM65x TRM: >> https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) >> >> Signed-off-by: Devarsh Thakkar <devarsht@ti.com> >> --- >> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 7 +++++-- >> 1 file changed, 5 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> index b6767ef0d24d..55e3e490d0e6 100644 >> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> @@ -37,6 +37,7 @@ properties: >> - description: OVR2 overlay manager for vp2 >> - description: VP1 video port 1 >> - description: VP2 video port 2 >> + - description: common1 DSS register area >> >> reg-names: >> items: >> @@ -47,6 +48,7 @@ properties: >> - const: ovr2 >> - const: vp1 >> - const: vp2 >> + - const: common1 >> >> clocks: >> items: >> @@ -147,9 +149,10 @@ examples: >> <0x04a07000 0x1000>, /* ovr1 */ >> <0x04a08000 0x1000>, /* ovr2 */ >> <0x04a0a000 0x1000>, /* vp1 */ >> - <0x04a0b000 0x1000>; /* vp2 */ >> + <0x04a0b000 0x1000>, /* vp2 */ >> + <0x04a01000 0x1000>; /* common1 */ >> reg-names = "common", "vidl1", "vid", >> - "ovr1", "ovr2", "vp1", "vp2"; >> + "ovr1", "ovr2", "vp1", "vp2", "common1"; >> ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; >> power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; >> clocks = <&k3_clks 67 1>, >> -- >> 2.34.1 >> ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add support for common1 region 2024-01-16 9:13 ` Devarsh Thakkar @ 2024-01-16 9:36 ` Conor Dooley 0 siblings, 0 replies; 13+ messages in thread From: Conor Dooley @ 2024-01-16 9:36 UTC (permalink / raw) To: Devarsh Thakkar Cc: Conor Dooley, jyri.sarha, tomi.valkeinen, airlied, daniel, maarten.lankhorst, mripard, tzimmermann, robh+dt, krzysztof.kozlowski+dt, conor+dt, dri-devel, devicetree, linux-kernel, praneeth, nm, vigneshr, a-bhatia1, j-luthra, kristo [-- Attachment #1: Type: text/plain, Size: 653 bytes --] On Tue, Jan 16, 2024 at 02:43:25PM +0530, Devarsh Thakkar wrote: > Hi Conor, > > Thanks for the review. > > On 15/01/24 21:47, Conor Dooley wrote: > > On Mon, Jan 15, 2024 at 06:27:15PM +0530, Devarsh Thakkar wrote: > >> TI keystone display subsystem present in AM65 and other SoCs such as AM62 > > > > Do all 3 SoCs supported by this binding (am625 am62a7 am65x) have this > > common1 register? If not, you should limit it the platforms that do have > > it. > > > > Yes all 3 SoCs supported by binding have common1 register space supported. Okay, thanks. Acked-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add support for common1 region 2024-01-15 12:57 ` [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add support for common1 region Devarsh Thakkar 2024-01-15 16:17 ` Conor Dooley @ 2024-02-14 9:10 ` Tomi Valkeinen 2024-02-14 9:23 ` Tomi Valkeinen 1 sibling, 1 reply; 13+ messages in thread From: Tomi Valkeinen @ 2024-02-14 9:10 UTC (permalink / raw) To: Devarsh Thakkar Cc: praneeth, nm, vigneshr, a-bhatia1, j-luthra, kristo, jyri.sarha, airlied, daniel, maarten.lankhorst, mripard, tzimmermann, robh+dt, krzysztof.kozlowski+dt, conor+dt, dri-devel, devicetree, linux-kernel Hi, On 15/01/2024 14:57, Devarsh Thakkar wrote: > TI keystone display subsystem present in AM65 and other SoCs such as AM62 > support two separate register spaces namely "common" and "common1" which > can be used by two separate hosts to program the display controller as > described in respective Technical Reference Manuals [1]. > > The common1 register space has similar set of configuration registers as > supported in common register space except the global configuration > registers which are exclusive to common region. > > This adds binding for "common1" register region too as supported by the > hardware. > > [1]: > AM62x TRM: > https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) > > AM65x TRM: > https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) > > Signed-off-by: Devarsh Thakkar <devarsht@ti.com> > --- > .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > index b6767ef0d24d..55e3e490d0e6 100644 > --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > @@ -37,6 +37,7 @@ properties: > - description: OVR2 overlay manager for vp2 > - description: VP1 video port 1 > - description: VP2 video port 2 > + - description: common1 DSS register area > > reg-names: > items: > @@ -47,6 +48,7 @@ properties: > - const: ovr2 > - const: vp1 > - const: vp2 > + - const: common1 > > clocks: > items: > @@ -147,9 +149,10 @@ examples: > <0x04a07000 0x1000>, /* ovr1 */ > <0x04a08000 0x1000>, /* ovr2 */ > <0x04a0a000 0x1000>, /* vp1 */ > - <0x04a0b000 0x1000>; /* vp2 */ > + <0x04a0b000 0x1000>, /* vp2 */ > + <0x04a01000 0x1000>; /* common1 */ > reg-names = "common", "vidl1", "vid", > - "ovr1", "ovr2", "vp1", "vp2"; > + "ovr1", "ovr2", "vp1", "vp2", "common1"; > ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; > power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 67 1>, Looks fine to me, I'll apply to drm-misc-next. Tomi ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add support for common1 region 2024-02-14 9:10 ` Tomi Valkeinen @ 2024-02-14 9:23 ` Tomi Valkeinen 2024-02-14 11:23 ` Devarsh Thakkar 0 siblings, 1 reply; 13+ messages in thread From: Tomi Valkeinen @ 2024-02-14 9:23 UTC (permalink / raw) To: Devarsh Thakkar, conor+dt, krzysztof.kozlowski+dt, robh+dt Cc: praneeth, nm, vigneshr, a-bhatia1, j-luthra, kristo, jyri.sarha, airlied, daniel, maarten.lankhorst, mripard, tzimmermann, dri-devel, devicetree, linux-kernel On 14/02/2024 11:10, Tomi Valkeinen wrote: > Hi, > > On 15/01/2024 14:57, Devarsh Thakkar wrote: >> TI keystone display subsystem present in AM65 and other SoCs such as AM62 >> support two separate register spaces namely "common" and "common1" which >> can be used by two separate hosts to program the display controller as >> described in respective Technical Reference Manuals [1]. >> >> The common1 register space has similar set of configuration registers as >> supported in common register space except the global configuration >> registers which are exclusive to common region. >> >> This adds binding for "common1" register region too as supported by the >> hardware. >> >> [1]: >> AM62x TRM: >> https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) >> >> AM65x TRM: >> https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) >> >> Signed-off-by: Devarsh Thakkar <devarsht@ti.com> >> --- >> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 7 +++++-- >> 1 file changed, 5 insertions(+), 2 deletions(-) >> >> diff --git >> a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> index b6767ef0d24d..55e3e490d0e6 100644 >> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> @@ -37,6 +37,7 @@ properties: >> - description: OVR2 overlay manager for vp2 >> - description: VP1 video port 1 >> - description: VP2 video port 2 >> + - description: common1 DSS register area >> reg-names: >> items: >> @@ -47,6 +48,7 @@ properties: >> - const: ovr2 >> - const: vp1 >> - const: vp2 >> + - const: common1 >> clocks: >> items: >> @@ -147,9 +149,10 @@ examples: >> <0x04a07000 0x1000>, /* ovr1 */ >> <0x04a08000 0x1000>, /* ovr2 */ >> <0x04a0a000 0x1000>, /* vp1 */ >> - <0x04a0b000 0x1000>; /* vp2 */ >> + <0x04a0b000 0x1000>, /* vp2 */ >> + <0x04a01000 0x1000>; /* common1 */ >> reg-names = "common", "vidl1", "vid", >> - "ovr1", "ovr2", "vp1", "vp2"; >> + "ovr1", "ovr2", "vp1", "vp2", "common1"; >> ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; >> power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; >> clocks = <&k3_clks 67 1>, > > Looks fine to me, I'll apply to drm-misc-next. Hmm, now thinking about this, doesn't this cause dtb checks to start failing, as the dtbs are missing one entry? Is it better to merge these kind of changes with the dts changes? Or does it matter? Tomi ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add support for common1 region 2024-02-14 9:23 ` Tomi Valkeinen @ 2024-02-14 11:23 ` Devarsh Thakkar 0 siblings, 0 replies; 13+ messages in thread From: Devarsh Thakkar @ 2024-02-14 11:23 UTC (permalink / raw) To: Tomi Valkeinen, conor+dt, krzysztof.kozlowski+dt, robh+dt, Raghavendra, Vignesh Cc: praneeth, nm, vigneshr, a-bhatia1, j-luthra, kristo, jyri.sarha, airlied, daniel, maarten.lankhorst, mripard, tzimmermann, dri-devel, devicetree, linux-kernel, devarsht Hi Tomi, Vignesh, On 14/02/24 14:53, Tomi Valkeinen wrote: > On 14/02/2024 11:10, Tomi Valkeinen wrote: >> Hi, >> >> On 15/01/2024 14:57, Devarsh Thakkar wrote: >>> TI keystone display subsystem present in AM65 and other SoCs such as AM62 >>> support two separate register spaces namely "common" and "common1" which >>> can be used by two separate hosts to program the display controller as >>> described in respective Technical Reference Manuals [1]. >>> >>> The common1 register space has similar set of configuration registers as >>> supported in common register space except the global configuration >>> registers which are exclusive to common region. >>> >>> This adds binding for "common1" register region too as supported by the >>> hardware. >>> >>> [1]: >>> AM62x TRM: >>> https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) >>> >>> AM65x TRM: >>> https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) >>> >>> Signed-off-by: Devarsh Thakkar <devarsht@ti.com> >>> --- >>> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 7 +++++-- >>> 1 file changed, 5 insertions(+), 2 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >>> b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >>> index b6767ef0d24d..55e3e490d0e6 100644 >>> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >>> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >>> @@ -37,6 +37,7 @@ properties: >>> - description: OVR2 overlay manager for vp2 >>> - description: VP1 video port 1 >>> - description: VP2 video port 2 >>> + - description: common1 DSS register area >>> reg-names: >>> items: >>> @@ -47,6 +48,7 @@ properties: >>> - const: ovr2 >>> - const: vp1 >>> - const: vp2 >>> + - const: common1 >>> clocks: >>> items: >>> @@ -147,9 +149,10 @@ examples: >>> <0x04a07000 0x1000>, /* ovr1 */ >>> <0x04a08000 0x1000>, /* ovr2 */ >>> <0x04a0a000 0x1000>, /* vp1 */ >>> - <0x04a0b000 0x1000>; /* vp2 */ >>> + <0x04a0b000 0x1000>, /* vp2 */ >>> + <0x04a01000 0x1000>; /* common1 */ >>> reg-names = "common", "vidl1", "vid", >>> - "ovr1", "ovr2", "vp1", "vp2"; >>> + "ovr1", "ovr2", "vp1", "vp2", "common1"; >>> ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; >>> power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; >>> clocks = <&k3_clks 67 1>, >> >> Looks fine to me, I'll apply to drm-misc-next. > > Hmm, now thinking about this, doesn't this cause dtb checks to start failing, > as the dtbs are missing one entry? Is it better to merge these kind of changes > with the dts changes? Or does it matter? > Yes if one get's applied and other doesn't then there will be such issues. I am sending shortly both the dt-binding and device-tree patches together, as long as both look fine and ready to be accepted by respective maintainers, I think both can get merged to respective trees and land in linux-next without causing any issues. Regards Devarsh > Tomi > ^ permalink raw reply [flat|nested] 13+ messages in thread
* [DO NOT MERGE PATCH 2/2] arm64: dts: ti: Add common1 register space for AM62x and AM65x SoCs 2024-01-15 12:57 [PATCH 0/2] Add common1 register space for TI Keystone displays Devarsh Thakkar 2024-01-15 12:57 ` [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add support for common1 region Devarsh Thakkar @ 2024-01-15 12:57 ` Devarsh Thakkar 2024-01-15 16:14 ` Conor Dooley 1 sibling, 1 reply; 13+ messages in thread From: Devarsh Thakkar @ 2024-01-15 12:57 UTC (permalink / raw) To: jyri.sarha, tomi.valkeinen, airlied, daniel, maarten.lankhorst, mripard, tzimmermann, robh+dt, krzysztof.kozlowski+dt, conor+dt, dri-devel, devicetree, linux-kernel Cc: praneeth, nm, vigneshr, a-bhatia1, j-luthra, kristo, devarsht This adds common1 register space for AM62x and AM65x SoC's which are using TI's Keystone display hardware and supporting it as described in Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml. This region is documented in respective Technical Reference Manuals [1]. [1]: AM62x TRM: https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) AM65x TRM: https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) Signed-off-by: Devarsh Thakkar <devarsht@ti.com> --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 464b7565d085..298bf8d5de8c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -779,9 +779,10 @@ dss: dss@30200000 { <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 186 6>, <&dss_vp1_clk>, diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index fcea54465636..5b2d4365b911 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -1019,9 +1019,10 @@ dss: dss@4a00000 { <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ + <0x0 0x04a01000 0x0 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [DO NOT MERGE PATCH 2/2] arm64: dts: ti: Add common1 register space for AM62x and AM65x SoCs 2024-01-15 12:57 ` [DO NOT MERGE PATCH 2/2] arm64: dts: ti: Add common1 register space for AM62x and AM65x SoCs Devarsh Thakkar @ 2024-01-15 16:14 ` Conor Dooley 2024-01-16 9:18 ` Devarsh Thakkar 0 siblings, 1 reply; 13+ messages in thread From: Conor Dooley @ 2024-01-15 16:14 UTC (permalink / raw) To: Devarsh Thakkar Cc: jyri.sarha, tomi.valkeinen, airlied, daniel, maarten.lankhorst, mripard, tzimmermann, robh+dt, krzysztof.kozlowski+dt, conor+dt, dri-devel, devicetree, linux-kernel, praneeth, nm, vigneshr, a-bhatia1, j-luthra, kristo [-- Attachment #1: Type: text/plain, Size: 2630 bytes --] On Mon, Jan 15, 2024 at 06:27:16PM +0530, Devarsh Thakkar wrote: > This adds common1 register space for AM62x and AM65x SoC's which are using > TI's Keystone display hardware and supporting it as described in > Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml. > > This region is documented in respective Technical Reference Manuals [1]. > > [1]: > AM62x TRM: > https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) > > AM65x TRM: > https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) > > Signed-off-by: Devarsh Thakkar <devarsht@ti.com> > --- "[DO NOT MERGE PATCH 2/2]" but no rationale here as to why this cannot be merged? What's the problem with it? Cheers, Conor. > arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 5 +++-- > arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++-- > 2 files changed, 6 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > index 464b7565d085..298bf8d5de8c 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > @@ -779,9 +779,10 @@ dss: dss@30200000 { > <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ > <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ > <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ > - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ > + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ > + <0x00 0x30201000 0x00 0x1000>; /* common1 */ > reg-names = "common", "vidl1", "vid", > - "ovr1", "ovr2", "vp1", "vp2"; > + "ovr1", "ovr2", "vp1", "vp2", "common1"; > power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 186 6>, > <&dss_vp1_clk>, > diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > index fcea54465636..5b2d4365b911 100644 > --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > @@ -1019,9 +1019,10 @@ dss: dss@4a00000 { > <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ > <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ > <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ > - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ > + <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ > + <0x0 0x04a01000 0x0 0x1000>; /* common1 */ > reg-names = "common", "vidl1", "vid", > - "ovr1", "ovr2", "vp1", "vp2"; > + "ovr1", "ovr2", "vp1", "vp2", "common1"; > > ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; > > -- > 2.34.1 > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [DO NOT MERGE PATCH 2/2] arm64: dts: ti: Add common1 register space for AM62x and AM65x SoCs 2024-01-15 16:14 ` Conor Dooley @ 2024-01-16 9:18 ` Devarsh Thakkar 2024-01-16 9:38 ` Conor Dooley 2024-01-16 14:05 ` Rob Herring 0 siblings, 2 replies; 13+ messages in thread From: Devarsh Thakkar @ 2024-01-16 9:18 UTC (permalink / raw) To: Conor Dooley Cc: jyri.sarha, tomi.valkeinen, airlied, daniel, maarten.lankhorst, mripard, tzimmermann, robh+dt, krzysztof.kozlowski+dt, conor+dt, dri-devel, devicetree, linux-kernel, praneeth, nm, vigneshr, a-bhatia1, j-luthra, kristo Hi Conor, Thanks for the review. On 15/01/24 21:44, Conor Dooley wrote: > On Mon, Jan 15, 2024 at 06:27:16PM +0530, Devarsh Thakkar wrote: >> This adds common1 register space for AM62x and AM65x SoC's which are using >> TI's Keystone display hardware and supporting it as described in >> Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml. >> >> This region is documented in respective Technical Reference Manuals [1]. >> >> [1]: >> AM62x TRM: >> https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) >> >> AM65x TRM: >> https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) >> >> Signed-off-by: Devarsh Thakkar <devarsht@ti.com> >> --- > > "[DO NOT MERGE PATCH 2/2]" but no rationale here as to why this cannot > be merged? What's the problem with it? > No problem as such from my point of view, but this is the process I follow since maintainer trees for device-tree file and bindings are different. I generally mark a [DO NOT MERGE] tag for device-tree file patches until binding patch gets merged so that the device-tree patches don't get applied by mistake if binding patch has some pending comments. Once binding patch gets merged, I re-send the device-tree file patches again to respective list. Regards Devarsh > Cheers, > Conor. > >> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 5 +++-- >> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++-- >> 2 files changed, 6 insertions(+), 4 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi >> index 464b7565d085..298bf8d5de8c 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi >> @@ -779,9 +779,10 @@ dss: dss@30200000 { >> <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ >> <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ >> <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ >> - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ >> + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ >> + <0x00 0x30201000 0x00 0x1000>; /* common1 */ >> reg-names = "common", "vidl1", "vid", >> - "ovr1", "ovr2", "vp1", "vp2"; >> + "ovr1", "ovr2", "vp1", "vp2", "common1"; >> power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; >> clocks = <&k3_clks 186 6>, >> <&dss_vp1_clk>, >> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi >> index fcea54465636..5b2d4365b911 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi >> @@ -1019,9 +1019,10 @@ dss: dss@4a00000 { >> <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ >> <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ >> <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ >> - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ >> + <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ >> + <0x0 0x04a01000 0x0 0x1000>; /* common1 */ >> reg-names = "common", "vidl1", "vid", >> - "ovr1", "ovr2", "vp1", "vp2"; >> + "ovr1", "ovr2", "vp1", "vp2", "common1"; >> >> ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; >> >> -- >> 2.34.1 >> ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [DO NOT MERGE PATCH 2/2] arm64: dts: ti: Add common1 register space for AM62x and AM65x SoCs 2024-01-16 9:18 ` Devarsh Thakkar @ 2024-01-16 9:38 ` Conor Dooley 2024-01-16 14:05 ` Rob Herring 1 sibling, 0 replies; 13+ messages in thread From: Conor Dooley @ 2024-01-16 9:38 UTC (permalink / raw) To: Devarsh Thakkar Cc: Conor Dooley, jyri.sarha, tomi.valkeinen, airlied, daniel, maarten.lankhorst, mripard, tzimmermann, robh+dt, krzysztof.kozlowski+dt, conor+dt, dri-devel, devicetree, linux-kernel, praneeth, nm, vigneshr, a-bhatia1, j-luthra, kristo [-- Attachment #1: Type: text/plain, Size: 1514 bytes --] On Tue, Jan 16, 2024 at 02:48:53PM +0530, Devarsh Thakkar wrote: > Hi Conor, > > Thanks for the review. > > On 15/01/24 21:44, Conor Dooley wrote: > > On Mon, Jan 15, 2024 at 06:27:16PM +0530, Devarsh Thakkar wrote: > >> This adds common1 register space for AM62x and AM65x SoC's which are using > >> TI's Keystone display hardware and supporting it as described in > >> Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml. > >> > >> This region is documented in respective Technical Reference Manuals [1]. > >> > >> [1]: > >> AM62x TRM: > >> https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) > >> > >> AM65x TRM: > >> https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) > >> > >> Signed-off-by: Devarsh Thakkar <devarsht@ti.com> > >> --- > > > > "[DO NOT MERGE PATCH 2/2]" but no rationale here as to why this cannot > > be merged? What's the problem with it? > > > > No problem as such from my point of view, but this is the process I follow > since maintainer trees for device-tree file and bindings are different. I > generally mark a [DO NOT MERGE] tag for device-tree file patches until binding > patch gets merged so that the device-tree patches don't get applied by mistake > if binding patch has some pending comments. > > Once binding patch gets merged, I re-send the device-tree file patches again > to respective list. I see. Please note this in your patches, under the --- line, in the future to avoid confusion. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [DO NOT MERGE PATCH 2/2] arm64: dts: ti: Add common1 register space for AM62x and AM65x SoCs 2024-01-16 9:18 ` Devarsh Thakkar 2024-01-16 9:38 ` Conor Dooley @ 2024-01-16 14:05 ` Rob Herring 1 sibling, 0 replies; 13+ messages in thread From: Rob Herring @ 2024-01-16 14:05 UTC (permalink / raw) To: Devarsh Thakkar Cc: Conor Dooley, jyri.sarha, tomi.valkeinen, airlied, daniel, maarten.lankhorst, mripard, tzimmermann, krzysztof.kozlowski+dt, conor+dt, dri-devel, devicetree, linux-kernel, praneeth, nm, vigneshr, a-bhatia1, j-luthra, kristo On Tue, Jan 16, 2024 at 02:48:53PM +0530, Devarsh Thakkar wrote: > Hi Conor, > > Thanks for the review. > > On 15/01/24 21:44, Conor Dooley wrote: > > On Mon, Jan 15, 2024 at 06:27:16PM +0530, Devarsh Thakkar wrote: > >> This adds common1 register space for AM62x and AM65x SoC's which are using > >> TI's Keystone display hardware and supporting it as described in > >> Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml. > >> > >> This region is documented in respective Technical Reference Manuals [1]. > >> > >> [1]: > >> AM62x TRM: > >> https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) > >> > >> AM65x TRM: > >> https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) > >> > >> Signed-off-by: Devarsh Thakkar <devarsht@ti.com> > >> --- > > > > "[DO NOT MERGE PATCH 2/2]" but no rationale here as to why this cannot > > be merged? What's the problem with it? > > > > No problem as such from my point of view, but this is the process I follow > since maintainer trees for device-tree file and bindings are different. I > generally mark a [DO NOT MERGE] tag for device-tree file patches until binding > patch gets merged so that the device-tree patches don't get applied by mistake > if binding patch has some pending comments. RFC is the tag for "don't merge". Don't make-up your own tags. Rob ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2024-02-14 11:23 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-01-15 12:57 [PATCH 0/2] Add common1 register space for TI Keystone displays Devarsh Thakkar 2024-01-15 12:57 ` [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add support for common1 region Devarsh Thakkar 2024-01-15 16:17 ` Conor Dooley 2024-01-16 9:13 ` Devarsh Thakkar 2024-01-16 9:36 ` Conor Dooley 2024-02-14 9:10 ` Tomi Valkeinen 2024-02-14 9:23 ` Tomi Valkeinen 2024-02-14 11:23 ` Devarsh Thakkar 2024-01-15 12:57 ` [DO NOT MERGE PATCH 2/2] arm64: dts: ti: Add common1 register space for AM62x and AM65x SoCs Devarsh Thakkar 2024-01-15 16:14 ` Conor Dooley 2024-01-16 9:18 ` Devarsh Thakkar 2024-01-16 9:38 ` Conor Dooley 2024-01-16 14:05 ` Rob Herring
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