From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail5.25mail.st (mail5.25mail.st [74.50.62.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 369F012B6B; Thu, 18 Jan 2024 08:56:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.50.62.9 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705568211; cv=none; b=om9c3oYFJEPNGniRjTPcq1swSSOe4TE97EOEY/OcFfbGFs3+zT73Pf36SdLfqf5hZN0kwRYU0wab+4rnwGbuTs+xzGYgQSdSCnaWaH6g8/YijBMJMR+xZFBqVdqasFKOVpzXsKlEzBH/vWFwSvdroYPGqO7WJxEkzWPzdrGAVag= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705568211; c=relaxed/simple; bh=vULAl46BBydQR4ps2jMZiFaBG2168vzYuRJQjRETXmM=; h=Received:DKIM-Signature:Date:From:To:Cc:Subject:Message-ID: References:MIME-Version:Content-Type:Content-Disposition: In-Reply-To; b=nhNn7IN6Skrow6ERuKY+PA5TEFhceeGkqX4dVPv2jRUkiVW3lcZaDf9l5RyUvKv6mRC9bUwstwb659M56L+f6hqpw/9kTAYKJpdxEdR4yVvnFJ13arHjj7r5rviX6FcUnm2qg5NM2pd6+6G/Q1BLHgjUcWhFlU9T1tID16qhWho= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=atomide.com; spf=fail smtp.mailfrom=atomide.com; dkim=pass (2048-bit key) header.d=atomide.com header.i=@atomide.com header.b=Gw04zt0W; arc=none smtp.client-ip=74.50.62.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=atomide.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=atomide.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=atomide.com header.i=@atomide.com header.b="Gw04zt0W" Received: from localhost (91-158-86-216.elisa-laajakaista.fi [91.158.86.216]) by mail5.25mail.st (Postfix) with ESMTPSA id 8CA6960547; Thu, 18 Jan 2024 08:55:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=atomide.com; s=25mailst; t=1705568209; bh=vULAl46BBydQR4ps2jMZiFaBG2168vzYuRJQjRETXmM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Gw04zt0Wpjy9eWoxk2lS2uRHPyetKndWTDy1xt3tVGx6vKHlNkOkWIOKrTzvdlw/9 66hcjRDA6awFbthpcjUwMl9Ag054ol8J7CDoqS8Ylxom3qRjvEEiO42kKCJd7piKXG /pBdyyWMFJWk62EFvYAkz/ET12d+9KZ1ZrUe4VIu/KG0WZBdK7YpSKhh2xshMli9/S gVVlFTKdKDM0zIga8bgoPdDQsFxhXBtVWbkeetqLrliFyg9Pu7b1qV6J7RCc90wGT2 zl6zEaNx93DQC83AFSlIeGXIbiPEfkOHUAzePS1mHU6/9kjkvMvgRKFiAOeMPcANkR mknuZHXKNV/qg== Date: Thu, 18 Jan 2024 10:55:51 +0200 From: Tony Lindgren To: Andrew Davis Cc: Frank Binns , Matt Coster , "H . Nikolaus Schaller" , Adam Ford , Ivaylo Dimitrov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?Q?Beno=C3=AEt?= Cousson , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Paul Cercueil , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-omap@vger.kernel.org, linux-mips@vger.kernel.org Subject: Re: [PATCH 08/11] ARM: dts: DRA7xx: Add device tree entry for SGX GPU Message-ID: <20240118085551.GQ5185@atomide.com> References: <20240109171950.31010-1-afd@ti.com> <20240109171950.31010-9-afd@ti.com> <20240110082924.GA5185@atomide.com> <55efd488-c6a0-4dca-baea-1fa93d13dd17@ti.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <55efd488-c6a0-4dca-baea-1fa93d13dd17@ti.com> * Andrew Davis [240117 15:52]: > On 1/10/24 2:29 AM, Tony Lindgren wrote: > > * Andrew Davis [240109 17:20]: > > > --- a/arch/arm/boot/dts/ti/omap/dra7.dtsi > > > +++ b/arch/arm/boot/dts/ti/omap/dra7.dtsi > > > @@ -850,12 +850,19 @@ target-module@56000000 { > > > ; > > > ti,sysc-sidle = , > > > , > > > - ; > > > + , > > > + ; > > > > You probably checked this already.. But just in case, can you please > > confirm this is intentional. The documentation lists the smart wakeup > > capability bit as reserved for dra7, maybe the documentation is wrong. > > > > It was an intentional change, although I'm not sure it is correct :) > > This is how we had it in our "evil vendor tree" for years (back when it > was hwmod based), so when converting these nodes to use "ti,sysc" I noticed > this bit was set, but as you point out the documentation disagrees. > > I'd rather go with what has worked before, but it doesn't seem to > break anything either way, so we could also break this change out into > its own patch if you would prefer. I agree it's best to stick what is known to work. How about let's add the related information to the patch description? Regards, Tony