[PATCH v2 0/7] MPFS clock fixes required for correct CAN clock modeling

Conor Dooley
2024-01-22T12:20:11Z

From: Conor Dooley <conor.dooley@microchip.com>

While reviewing a CAN driver internally for MPFS [1], I realised
that the modeling of the MSSPLL such that only one of its outputs could
be used was not correct. The CAN controllers on MPFS take 2 input
clocks - one that is the bus clock, acquired from the main MSSPLL and
a second clock for the AHB interface to the result of the SoC.
Currently the binding for the CAN controllers and the represetnation
of the MSSPLL only allows for one of these clocks.
Modify the binding and devicetree to expect two clocks and rework the
main clock controller driver for MPFS such that it is capable of
providing multiple outputs from the MSSPLL.

Cheers,
Conor.

1 - Hopefully that'll show up on the lists soon, once we are happy with
it ourselves. (As of v2, that's not happened yet, Christmas etc gettin
in the way, soonTM).

Changes in v2:
- Swap MSSPLL out for MSSPLL0 in the driver, there's no functional
change there.
- drop the unneeded maxItems from clocks.

CC: Conor Dooley <conor.dooley@microchip.com>
CC: Daire McNamara <daire.mcnamara@microchip.com>
CC: Wolfgang Grandegger <wg@grandegger.com>
CC: Marc Kleine-Budde <mkl@pengutronix.de>
CC: "David S. Miller" <davem@davemloft.net>
CC: Eric Dumazet <edumazet@google.com>
CC: Jakub Kicinski <kuba@kernel.org>
CC: Paolo Abeni <pabeni@redhat.com>
CC: Rob Herring <robh+dt@kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
CC: Paul Walmsley <paul.walmsley@sifive.com>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: Albert Ou <aou@eecs.berkeley.edu>
CC: Michael Turquette <mturquette@baylibre.com>
CC: Stephen Boyd <sboyd@kernel.org>
CC: linux-riscv@lists.infradead.org
CC: linux-can@vger.kernel.org
CC: netdev@vger.kernel.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-clk@vger.kernel.org

Conor Dooley (7):
dt-bindings: clock: mpfs: add more MSSPLL output definitions
dt-bindings: can: mpfs: add missing required clock
clk: microchip: mpfs: split MSSPLL in two
clk: microchip: mpfs: setup for using other mss pll outputs
clk: microchip: mpfs: add missing MSSPLL outputs
clk: microchip: mpfs: convert MSSPLL outputs to clk_divider
riscv: dts: microchip: add missing CAN bus clocks

.../bindings/net/can/microchip,mpfs-can.yaml | 6 +-
arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 +-
drivers/clk/microchip/clk-mpfs.c | 154 ++++++++++--------
.../dt-bindings/clock/microchip,mpfs-clock.h | 5 +
4 files changed, 98 insertions(+), 71 deletions(-)

--
2.43.0