From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2C3C012BEA8; Wed, 31 Jan 2024 14:52:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706712773; cv=none; b=FajdmOrEPGMYULr8hwKJ/R7VzFMCDRsLYgSHyc8qRUygQIpSV1WEnusXy8keOQT9rn1DQD9/sI+JhRmT4THrLJ1NZpCY2MvDeWsfudDk3us5EU2xlRe8lTTSZ+NcJF5rXViWScrICnSb9sJoDplaGrizikAn2SbW2h+Ozdxh8TY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706712773; c=relaxed/simple; bh=Oogf3pucZYuTqQuJqbTDe2IY/fTSAT6FHkzSNlxg3ug=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MkXx6bS3tI4eE/r+dvxrB0fh2+TQH+C7BRwcY8ZyZVhrh7VZ99Zp32fNhWDZVhkjxDg3DzZswmSW1z+1urIyKcs0Eo6ZGTWKOi4hEHp1ljBkceNYnjOX8xnMKT28uVmg/h1Jqm0Mw4ZC/WkqEdN0WW+Cd3Khhw3T5yzKAUXOoIY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CF49EDA7; Wed, 31 Jan 2024 06:53:33 -0800 (PST) Received: from donnerap.manchester.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 89FDA3F762; Wed, 31 Jan 2024 06:52:47 -0800 (PST) Date: Wed, 31 Jan 2024 14:52:44 +0000 From: Andre Przywara To: Aleksandr Shubin Cc: linux-kernel@vger.kernel.org, Conor Dooley , Uwe =?UTF-8?B?S2xlaW5lLUvDtm5pZw==?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Marc Kleine-Budde , Maksim Kiselev , Cristian Ciocaltea , John Watts , Cheo Fusi , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: Re: [PATCH v8 1/3] dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM controller Message-ID: <20240131145244.4f534bac@donnerap.manchester.arm.com> In-Reply-To: <20240131125920.2879433-2-privatesub2@gmail.com> References: <20240131125920.2879433-1-privatesub2@gmail.com> <20240131125920.2879433-2-privatesub2@gmail.com> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 31 Jan 2024 15:59:14 +0300 Aleksandr Shubin wrote: Hi, > Allwinner's D1, T113-S3 and R329 SoCs have a new pwm > controller witch is different from the previous pwm-sun4i. > > The D1 and T113 are identical in terms of peripherals, > they differ only in the architecture of the CPU core, and > even share the majority of their DT. Because of that, > using the same compatible makes sense. > The R329 is a different SoC though, and should have > a different compatible string added, especially as there > is a difference in the number of channels. > > D1 and T113s SoCs have one PWM controller with 8 channels. > R329 SoC has two PWM controllers in both power domains, one of > them has 9 channels (CPUX one) and the other has 6 (CPUS one). > > Add a device tree binding for them. > > Signed-off-by: Aleksandr Shubin > Reviewed-by: Conor Dooley > --- > .../bindings/pwm/allwinner,sun20i-pwm.yaml | 88 +++++++++++++++++++ > 1 file changed, 88 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > new file mode 100644 > index 000000000000..716f75776006 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > @@ -0,0 +1,88 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Allwinner D1, T113-S3 and R329 PWM > + > +maintainers: > + - Aleksandr Shubin > + - Brandon Cheo Fusi > + > +properties: > + compatible: > + oneOf: > + - const: allwinner,sun20i-d1-pwm > + - items: > + - const: allwinner,sun20i-r329-pwm > + - const: allwinner,sun20i-d1-pwm > + > + reg: > + maxItems: 1 > + > + "#pwm-cells": > + const: 3 > + > + clocks: > + items: > + - description: Bus clock > + - description: 24 MHz oscillator > + - description: APB0 clock > + > + clock-names: > + items: > + - const: bus > + - const: hosc > + - const: apb0 > + > + resets: > + maxItems: 1 > + > + allwinner,pwm-channels: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: The number of PWM channels configured for this instance > + enum: [6, 9] > + > +allOf: > + - $ref: pwm.yaml# > + > + - if: > + properties: > + compatible: > + contains: > + const: allwinner,sun20i-r329-pwm > + > + then: > + required: > + - allwinner,pwm-channels > + > + else: > + properties: > + allwinner,pwm-channels: false Do we really need to be that strict? If something compatible to D1 pops up in the future, just with a different number of channels, we would need a new compatible string. If we would leave this else branch out, we could just specify some number differing from the default, and be good. The number of channels really looks like a parameter to the IP, it's modelled like this in the manual (PCR: 0x0100 + 0x0000 + N * 0x0020). Cheers, Andre > + > +unevaluatedProperties: false > + > +required: > + - compatible > + - reg > + - "#pwm-cells" > + - clocks > + - clock-names > + - resets > + > +examples: > + - | > + #include > + #include > + > + pwm: pwm@2000c00 { > + compatible = "allwinner,sun20i-d1-pwm"; > + reg = <0x02000c00 0x400>; > + clocks = <&ccu CLK_BUS_PWM>, <&dcxo>, <&ccu CLK_APB0>; > + clock-names = "bus", "hosc", "apb0"; > + resets = <&ccu RST_BUS_PWM>; > + #pwm-cells = <0x3>; > + }; > + > +...