From: Rob Herring <robh@kernel.org>
To: Markus Schneider-Pargmann <msp@baylibre.com>
Cc: Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
Santosh Shilimkar <ssantosh@kernel.org>,
Andrew Davis <afd@ti.com>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells
Date: Tue, 6 Feb 2024 18:43:05 +0000 [thread overview]
Message-ID: <20240206184305.GA1875492-robh@kernel.org> (raw)
In-Reply-To: <20240206143711.2410135-3-msp@baylibre.com>
On Tue, Feb 06, 2024 at 03:37:09PM +0100, Markus Schneider-Pargmann wrote:
> The information k3-socinfo requires is stored in an efuse area. This
> area is required by other devices/drivers as well, so using nvmem-cells
> can be a cleaner way to describe which information are used.
>
> If nvmem-cells are supplied, the address range is not required.
> Cells chipvariant, chippartno and chipmanufacturer are introduced to
> cover all required information.
>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> Reviewed-by: Andrew Davis <afd@ti.com>
> ---
> .../bindings/hwinfo/ti,k3-socinfo.yaml | 23 ++++++++++++++++++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> index dada28b47ea0..f085b7275b7d 100644
> --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> @@ -26,9 +26,24 @@ properties:
> reg:
> maxItems: 1
>
> + nvmem-cells:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> +
> + nvmem-cell-names:
> + items:
> + - const: chipvariant
> + - const: chippartno
> + - const: chipmanufacturer
> +
> required:
> - compatible
> - - reg
> +
> +oneOf:
> + - required:
> + - reg
> + - required:
> + - nvmem-cells
> + - nvmem-cell-names
>
> additionalProperties: false
>
> @@ -38,3 +53,9 @@ examples:
> compatible = "ti,am654-chipid";
> reg = <0x43000014 0x4>;
> };
> + - |
> + chipid: chipid@14 {
> + compatible = "ti,am654-chipid";
This isn't compatible if you have a completely different way to access
it.
> + nvmem-cells = <&chip_variant>, <&chip_partno>, <&chip_manufacturer>;
> + nvmem-cell-names = "chipvariant", "chippartno", "chipmanufacturer";
> + };
> --
> 2.43.0
>
next prev parent reply other threads:[~2024-02-06 18:43 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-06 14:37 [PATCH 0/4] soc: ti: k3-socinfo: Add support for nvmem cells Markus Schneider-Pargmann
2024-02-06 14:37 ` [PATCH 1/4] nvmem: core: Read into buffers larger than data Markus Schneider-Pargmann
2024-02-06 22:07 ` Srinivas Kandagatla
2024-02-06 14:37 ` [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells Markus Schneider-Pargmann
2024-02-06 18:23 ` Rob Herring
2024-02-06 18:43 ` Rob Herring [this message]
2024-02-14 9:31 ` Markus Schneider-Pargmann
2024-02-17 14:25 ` Krzysztof Kozlowski
2024-03-04 10:36 ` Markus Schneider-Pargmann
2024-03-05 7:43 ` Krzysztof Kozlowski
2024-03-05 11:17 ` Markus Schneider-Pargmann
2024-03-05 14:11 ` Krzysztof Kozlowski
2024-03-05 14:42 ` Andrew Davis
2024-03-05 17:01 ` Krzysztof Kozlowski
2024-03-05 17:41 ` Andrew Davis
2024-03-18 16:10 ` Markus Schneider-Pargmann
2024-02-07 7:58 ` Krzysztof Kozlowski
2024-02-06 14:37 ` [PATCH 3/4] soc: ti: k3-socinfo: Add support for nvmem cells Markus Schneider-Pargmann
2024-02-06 14:37 ` [PATCH 4/4] arm64: dts: ti: k3-am62-wakeup: Add chip efuse nodes Markus Schneider-Pargmann
2024-02-06 17:48 ` Andrew Davis
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