From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7555A168A8; Sun, 11 Feb 2024 23:40:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707694843; cv=none; b=pjUj9jTkN9v0hbxt++2A5fZvhcBk3FQiuPTvcSmlfplClESy0Snrol5VdFqqdyfhrAIclYyhInxK8oYhx3HxMKhxLs0tvV9D6SX/HXVYQ5M/L5lkJAAPEMDGEJBK/0Ij9Hu8yR/7U8pxzY/fMTGaPFLTHjyxDRkY8tXLI03kpRg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707694843; c=relaxed/simple; bh=atUs5qVxD+K/cG67yr9B5GRtKhk/D0bQa5VI06ZesN0=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gHkOvx6dXHSmsjKcvMd7XFTZ0fGUh7yz2+cn3sJvUHkFE1k1ORlKdbLzWKL7jRGZ75hknMyUYWyOxdGx17tGsCrvR6qDYwDmOrcf1cGRgIQMRGBKinb/6GYq+loIL+5N61rLivW71W3YgHgL3p7gfZF5oQrOYTAoAD/IaaNbc/k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 04CBFDA7; Sun, 11 Feb 2024 15:41:20 -0800 (PST) Received: from minigeek.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D0FC23F5A1; Sun, 11 Feb 2024 15:40:36 -0800 (PST) Date: Sun, 11 Feb 2024 23:39:26 +0000 From: Andre Przywara To: Jisheng Zhang Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 2/2] arm64: dts: allwinner: h616: Add Sipeed Longan SoM 3H and Pi 3H board support Message-ID: <20240211233926.70b327b1@minigeek.lan> In-Reply-To: <20240211081739.395-3-jszhang@kernel.org> References: <20240211081739.395-1-jszhang@kernel.org> <20240211081739.395-3-jszhang@kernel.org> Organization: Arm Ltd. X-Mailer: Claws Mail 4.2.0 (GTK 3.24.31; x86_64-slackware-linux-gnu) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Sun, 11 Feb 2024 16:17:39 +0800 Jisheng Zhang wrote: Hi Jisheng, thanks for the changes, and for spotting the 5V/3.3V issue yourself, which I missed. This looks good to me now. > The Sipeed Longan SoM 3H is a system on module based on the Allwinner > H618 SoC. The SoM features: > > - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU > - 2/4 GiB LPDDR4 DRAM SoMs > - AXP313a PMIC > - eMMC > > The Sipeed Longan PI 3H is a development board based on the above SoM. > The board features: > - Longan SoM 3H > - Raspberry-Pi-1 compatible GPIO header > - 2 USB 2.0 host port > - 1 USB 2.0 type C port (power supply + OTG) > - MicroSD slot > - 1Gbps Ethernet port (via RTL8211 PHY) > - HDMI port > - WiFi/BT chip > > Add the devicetree file describing the currently supported features, > namely PMIC, LEDs, UART, SD card, eMMC, USB and Ethernet. > > Signed-off-by: Jisheng Zhang Reviewed-by: Andre Przywara Cheers, Andre > --- > arch/arm64/boot/dts/allwinner/Makefile | 1 + > .../sun50i-h618-longan-module-3h.dtsi | 75 +++++++++ > .../dts/allwinner/sun50i-h618-longanpi-3h.dts | 144 ++++++++++++++++++ > 3 files changed, 220 insertions(+) > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.dts > > diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile > index 91d505b385de..4b9173a16efe 100644 > --- a/arch/arm64/boot/dts/allwinner/Makefile > +++ b/arch/arm64/boot/dts/allwinner/Makefile > @@ -42,5 +42,6 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-manta.dtb > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-pi.dtb > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb > +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-longanpi-3h.dtb > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-transpeed-8k618-t.dtb > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi > new file mode 100644 > index 000000000000..8c1263a3939e > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi > @@ -0,0 +1,75 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) Jisheng Zhang > + */ > + > +#include "sun50i-h616.dtsi" > + > +&mmc2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&mmc2_pins>; > + vmmc-supply = <®_dldo1>; > + vqmmc-supply = <®_aldo1>; > + bus-width = <8>; > + non-removable; > + cap-mmc-hw-reset; > + mmc-ddr-1_8v; > + mmc-hs200-1_8v; > + status = "okay"; > +}; > + > +&r_i2c { > + status = "okay"; > + > + axp313: pmic@36 { > + compatible = "x-powers,axp313a"; > + reg = <0x36>; > + #interrupt-cells = <1>; > + interrupt-controller; > + > + regulators { > + reg_aldo1: aldo1 { > + regulator-always-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-name = "vcc-1v8-pll"; > + }; > + > + reg_dldo1: dldo1 { > + regulator-always-on; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-name = "vcc-3v3-io"; > + }; > + > + reg_dcdc1: dcdc1 { > + regulator-always-on; > + regulator-min-microvolt = <810000>; > + regulator-max-microvolt = <990000>; > + regulator-name = "vdd-gpu-sys"; > + }; > + > + reg_dcdc2: dcdc2 { > + regulator-always-on; > + regulator-min-microvolt = <810000>; > + regulator-max-microvolt = <1100000>; > + regulator-name = "vdd-cpu"; > + }; > + > + reg_dcdc3: dcdc3 { > + regulator-always-on; > + regulator-min-microvolt = <1100000>; > + regulator-max-microvolt = <1100000>; > + regulator-name = "vdd-dram"; > + }; > + }; > + }; > +}; > + > +&pio { > + vcc-pc-supply = <®_dldo1>; > + vcc-pf-supply = <®_dldo1>; > + vcc-pg-supply = <®_aldo1>; > + vcc-ph-supply = <®_dldo1>; > + vcc-pi-supply = <®_dldo1>; > +}; > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.dts > new file mode 100644 > index 000000000000..18b29c6b867f > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-longanpi-3h.dts > @@ -0,0 +1,144 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) Jisheng Zhang > + */ > + > +/dts-v1/; > + > +#include "sun50i-h618-longan-module-3h.dtsi" > + > +#include > +#include > +#include > + > +/ { > + model = "Sipeed Longan Pi 3H"; > + compatible = "sipeed,longan-pi-3h", "sipeed,longan-module-3h", "allwinner,sun50i-h618"; > + > + aliases { > + ethernet0 = &emac0; > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + leds { > + compatible = "gpio-leds"; > + > + led-0 { > + color = ; > + function = LED_FUNCTION_INDICATOR; > + function-enumerator = <0>; > + gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ > + }; > + > + led-1 { > + color = ; > + function = LED_FUNCTION_INDICATOR; > + function-enumerator = <1>; > + gpios = <&pio 6 4 GPIO_ACTIVE_LOW>; /* PG4 */ > + }; > + }; > + > + reg_vcc5v: regulator-vcc5v { > + /* board wide 5V supply directly from the USB-C socket */ > + compatible = "regulator-fixed"; > + regulator-name = "vcc-5v"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + }; > + > + reg_vcc3v3: regulator-vcc3v3 { > + compatible = "regulator-fixed"; > + regulator-name = "vcc-3v3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + vin-supply = <®_vcc5v>; > + }; > +}; > + > +&axp313 { > + vin1-supply = <®_vcc5v>; > + vin2-supply = <®_vcc5v>; > + vin3-supply = <®_vcc5v>; > +}; > + > +&ehci1 { > + status = "okay"; > +}; > + > +&ohci1 { > + status = "okay"; > +}; > + > +&ehci2 { > + status = "okay"; > +}; > + > +&ohci2 { > + status = "okay"; > +}; > + > +/* WiFi & BT combo module is connected to this Host */ > +&ehci3 { > + status = "okay"; > +}; > + > +&ohci3 { > + status = "okay"; > +}; > + > +&emac0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&ext_rgmii_pins>; > + phy-mode = "rgmii"; > + phy-handle = <&ext_rgmii_phy>; > + allwinner,rx-delay-ps = <3100>; > + allwinner,tx-delay-ps = <700>; > + phy-supply = <®_vcc3v3>; > + status = "okay"; > +}; > + > +&mdio0 { > + ext_rgmii_phy: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + }; > +}; > + > +&mmc0 { > + bus-width = <4>; > + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ > + vmmc-supply = <®_vcc3v3>; > + status = "okay"; > +}; > + > +&uart0 { > + status = "okay"; > +}; > + > +&usbotg { > + /* > + * PHY0 pins are connected to a USB-C socket, but a role switch > + * is not implemented: both CC pins are pulled to GND. > + * The VBUS pins power the device, so a fixed peripheral mode > + * is the best choice. > + * The board can be powered via GPIOs, in this case port0 *can* > + * act as a host (with a cable/adapter ignoring CC), as VBUS is > + * then provided by the GPIOs. Any user of this setup would > + * need to adjust the DT accordingly: dr_mode set to "host", > + * enabling OHCI0 and EHCI0. > + */ > + dr_mode = "peripheral"; > + status = "okay"; > +}; > + > +&usbphy { > + usb1_vbus-supply = <®_vcc5v>; > + usb2_vbus-supply = <®_vcc5v>; > + status = "okay"; > +};