From: Rob Herring <robh@kernel.org>
To: Chen Wang <unicorn_wang@outlook.com>
Cc: Chen Wang <unicornxw@gmail.com>,
aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
palmer@dabbelt.com, paul.walmsley@sifive.com,
richardcochran@gmail.com, sboyd@kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com,
guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com,
samuel.holland@sifive.com
Subject: Re: [PATCH v9 2/5] dt-bindings: clock: sophgo: add RP gate clocks for SG2042
Date: Mon, 12 Feb 2024 09:14:49 -0600 [thread overview]
Message-ID: <20240212151449.GA379868-robh@kernel.org> (raw)
In-Reply-To: <MA0P287MB2822C8930916B90A9C1BAA49FE462@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM>
On Tue, Feb 06, 2024 at 08:57:27PM +0800, Chen Wang wrote:
>
> On 2024/2/6 1:24, Rob Herring wrote:
> > On Fri, Feb 02, 2024 at 02:42:02PM +0800, Chen Wang wrote:
> > > From: Chen Wang <unicorn_wang@outlook.com>
> > >
> > > Add bindings for the gate clocks of RP subsystem for Sophgo SG2042.
> > >
> > > Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
> > > ---
> > > .../bindings/clock/sophgo,sg2042-rpgate.yaml | 37 ++++++++++++
> > > .../dt-bindings/clock/sophgo,sg2042-rpgate.h | 58 +++++++++++++++++++
> > > 2 files changed, 95 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml
> > > create mode 100644 include/dt-bindings/clock/sophgo,sg2042-rpgate.h
> > >
> > > diff --git a/Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml b/Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml
> > > new file mode 100644
> > > index 000000000000..69ce3a64f66c
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml
> > > @@ -0,0 +1,37 @@
> > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/clock/sophgo,sg2042-rpgate.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Sophgo SG2042 Gate Clock Generator for RP(riscv processors) subsystem
> > > +
> > > +maintainers:
> > > + - Chen Wang <unicorn_wang@outlook.com>
> > > +
> > > +properties:
> > > + compatible:
> > > + const: sophgo,sg2042-rpgate
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + '#clock-cells':
> > > + const: 1
> > > + description:
> > > + See <dt-bindings/clock/sophgo,sg2042-rpgate.h> for valid indices.
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - '#clock-cells'
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + clock-controller@10000000 {
> > > + compatible = "sophgo,sg2042-rpgate";
> > > + reg = <0x10000000 0x10000>;
> > > + #clock-cells = <1>;
> > No input clocks?
>
> I think it should have some input, I will add it, thanks.
>
> BTW, can we ignore this property if driver doesn't use it? In other words,
> do we have to add this clocks property just to indicate that this node
> requires some clocks as input from a hardware perspective?
Yes and no. The kernel will see the dependency and track that. But your
driver doesn't have to get the clock or anything. Though presumably the
source is a fixed-clock and you need its frequency to calculate child
clock rates.
Rob
next prev parent reply other threads:[~2024-02-12 15:14 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-02 6:39 [PATCH v9 0/5] riscv: sophgo: add clock support for sg2042 Chen Wang
2024-02-02 6:41 ` [PATCH v9 1/5] dt-bindings: clock: sophgo: add pll clocks for SG2042 Chen Wang
2024-02-05 17:22 ` Rob Herring
2024-02-02 6:42 ` [PATCH v9 2/5] dt-bindings: clock: sophgo: add RP gate " Chen Wang
2024-02-05 17:24 ` Rob Herring
2024-02-06 12:57 ` Chen Wang
2024-02-12 15:14 ` Rob Herring [this message]
2024-02-02 6:42 ` [PATCH v9 3/5] dt-bindings: clock: sophgo: add clkgen " Chen Wang
2024-02-02 6:42 ` [PATCH v9 4/5] clk: sophgo: Add SG2042 clock driver Chen Wang
2024-02-02 6:42 ` [PATCH v9 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC Chen Wang
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