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AJvYcCXcFuwrDVposcKRzkPbtkBFIPGxDhDiOg3JNina385AOrZ0aMNdxjRWIPH8Tv4knI8ReXfEay8idplZCR3uramo/6xZy4y+BRieLw== X-Gm-Message-State: AOJu0YzwEGfALdOAcmiGAG6giy2YefR2Dblm94k5ByDFIYWnfGM86T2k qzxlOOh3yVy6951uDW8+Dltes4Pcd/fho5lNSU89agWrYx/z8IOb9hUwJuSlIzQ= X-Google-Smtp-Source: AGHT+IEz0+A9x0GTcr1tO8p0VDE5KRpFc1BbSQ5HWLqCdx+AJgXr1jki3q4ZnbUMgc8MM5i0wwekUQ== X-Received: by 2002:a92:c54d:0:b0:365:1563:c4e5 with SMTP id a13-20020a92c54d000000b003651563c4e5mr2552537ilj.9.1708131506838; Fri, 16 Feb 2024 16:58:26 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d188-20020a6336c5000000b005dc89957e06sm487655pga.71.2024.02.16.16.58.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 16:58:26 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Adrian Hunter , Alexander Shishkin , Alexandre Ghiti , Andrew Jones , Anup Patel , Arnaldo Carvalho de Melo , Atish Patra , Christian Brauner , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Conor Dooley , devicetree@vger.kernel.org, Evan Green , Guo Ren , Heiko Stuebner , Ian Rogers , Ingo Molnar , James Clark , Jing Zhang , Jiri Olsa , Ji Sheng Teoh , John Garry , Jonathan Corbet , Kan Liang , Krzysztof Kozlowski , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, Ley Foon Tan , linux-doc@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Namhyung Kim , Palmer Dabbelt , Paul Walmsley , Peter Zijlstra , Rob Herring , Samuel Holland , Weilin Wang , Will Deacon , kaiwenxue1@gmail.com, Yang Jihong Subject: [PATCH RFC 05/20] RISC-V: Define indirect CSR access helpers Date: Fri, 16 Feb 2024 16:57:23 -0800 Message-Id: <20240217005738.3744121-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240217005738.3744121-1-atishp@rivosinc.com> References: <20240217005738.3744121-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The indriect CSR requires multiple instructions to read/write CSR. Add a few helper functions for ease of usage. Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr_ind.h | 42 ++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 arch/riscv/include/asm/csr_ind.h diff --git a/arch/riscv/include/asm/csr_ind.h b/arch/riscv/include/asm/csr_ind.h new file mode 100644 index 000000000000..9611c221eb6f --- /dev/null +++ b/arch/riscv/include/asm/csr_ind.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2024 Rivos Inc. + */ + +#ifndef _ASM_RISCV_CSR_IND_H +#define _ASM_RISCV_CSR_IND_H + +#include + +#define csr_ind_read(iregcsr, iselbase, iseloff) ({ \ + unsigned long value = 0; \ + unsigned long flags; \ + local_irq_save(flags); \ + csr_write(CSR_ISELECT, iselbase + iseloff); \ + value = csr_read(iregcsr); \ + local_irq_restore(flags); \ + value; \ +}) + +#define csr_ind_write(iregcsr, iselbase, iseloff, value) ({ \ + unsigned long flags; \ + local_irq_save(flags); \ + csr_write(CSR_ISELECT, iselbase + iseloff); \ + csr_write(iregcsr, value); \ + local_irq_restore(flags); \ +}) + +#define csr_ind_warl(iregcsr, iselbase, iseloff, warl_val) ({ \ + unsigned long old_val = 0, value = 0; \ + unsigned long flags; \ + local_irq_save(flags); \ + csr_write(CSR_ISELECT, iselbase + iseloff); \ + old_val = csr_read(iregcsr); \ + csr_write(iregcsr, value); \ + value = csr_read(iregcsr); \ + csr_write(iregcsr, old_val); \ + local_irq_restore(flags); \ + value; \ +}) + +#endif -- 2.34.1