* [PATCH 01/21] arm64: dts: qcom: sm8250: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
@ 2024-02-21 3:41 ` Manivannan Sadhasivam
2024-02-21 3:41 ` [PATCH 02/21] arm64: dts: qcom: sdm845: " Manivannan Sadhasivam
` (19 subsequent siblings)
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 760501c1301a..0c61623d9be9 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2197,6 +2197,16 @@ pcie0: pcie@1c00000 {
dma-coherent;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_phy: phy@1c06000 {
@@ -2298,6 +2308,16 @@ pcie1: pcie@1c08000 {
dma-coherent;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_phy: phy@1c0e000 {
@@ -2399,6 +2419,16 @@ pcie2: pcie@1c10000 {
dma-coherent;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie2_phy: phy@1c16000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 02/21] arm64: dts: qcom: sdm845: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
2024-02-21 3:41 ` [PATCH 01/21] arm64: dts: qcom: sm8250: Add PCIe bridge node Manivannan Sadhasivam
@ 2024-02-21 3:41 ` Manivannan Sadhasivam
2024-02-21 3:41 ` [PATCH 03/21] arm64: dts: qcom: sm8150: " Manivannan Sadhasivam
` (18 subsequent siblings)
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index c2244824355a..9a6e3bcdc5e4 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2375,6 +2375,16 @@ pcie0: pcie@1c00000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_phy: phy@1c06000 {
@@ -2479,6 +2489,16 @@ pcie1: pcie@1c08000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_phy: phy@1c0a000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 03/21] arm64: dts: qcom: sm8150: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
2024-02-21 3:41 ` [PATCH 01/21] arm64: dts: qcom: sm8250: Add PCIe bridge node Manivannan Sadhasivam
2024-02-21 3:41 ` [PATCH 02/21] arm64: dts: qcom: sdm845: " Manivannan Sadhasivam
@ 2024-02-21 3:41 ` Manivannan Sadhasivam
2024-02-21 3:41 ` [PATCH 04/21] arm64: dts: qcom: sm8350: " Manivannan Sadhasivam
` (17 subsequent siblings)
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 761a6757dc26..c9c46ccecb69 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1885,6 +1885,16 @@ pcie0: pcie@1c00000 {
pinctrl-0 = <&pcie0_default_state>;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_phy: phy@1c06000 {
@@ -1979,6 +1989,16 @@ pcie1: pcie@1c08000 {
pinctrl-0 = <&pcie1_default_state>;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_phy: phy@1c0e000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 04/21] arm64: dts: qcom: sm8350: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (2 preceding siblings ...)
2024-02-21 3:41 ` [PATCH 03/21] arm64: dts: qcom: sm8150: " Manivannan Sadhasivam
@ 2024-02-21 3:41 ` Manivannan Sadhasivam
2024-02-21 3:41 ` [PATCH 05/21] arm64: dts: qcom: sm8450: " Manivannan Sadhasivam
` (16 subsequent siblings)
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index e78c83a897c2..a2779c1bb4c1 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1566,6 +1566,16 @@ pcie0: pcie@1c00000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_phy: phy@1c06000 {
@@ -1649,6 +1659,16 @@ pcie1: pcie@1c08000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_phy: phy@1c0e000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 05/21] arm64: dts: qcom: sm8450: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (3 preceding siblings ...)
2024-02-21 3:41 ` [PATCH 04/21] arm64: dts: qcom: sm8350: " Manivannan Sadhasivam
@ 2024-02-21 3:41 ` Manivannan Sadhasivam
2024-02-21 12:46 ` neil.armstrong
2024-02-21 3:41 ` [PATCH 06/21] arm64: dts: qcom: sm8550: " Manivannan Sadhasivam
` (15 subsequent siblings)
20 siblings, 1 reply; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 01e4dfc4babd..e874cc4f8e6f 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1824,6 +1824,16 @@ pcie0: pcie@1c00000 {
pinctrl-0 = <&pcie0_default_state>;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_phy: phy@1c06000 {
@@ -1931,6 +1941,16 @@ pcie1: pcie@1c08000 {
pinctrl-0 = <&pcie1_default_state>;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_phy: phy@1c0e000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 05/21] arm64: dts: qcom: sm8450: Add PCIe bridge node
2024-02-21 3:41 ` [PATCH 05/21] arm64: dts: qcom: sm8450: " Manivannan Sadhasivam
@ 2024-02-21 12:46 ` neil.armstrong
0 siblings, 0 replies; 30+ messages in thread
From: neil.armstrong @ 2024-02-21 12:46 UTC (permalink / raw)
To: Manivannan Sadhasivam, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel
On 21/02/2024 04:41, Manivannan Sadhasivam wrote:
> On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
> for each controller instance. Hence, add a node to represent the bridge.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 01e4dfc4babd..e874cc4f8e6f 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -1824,6 +1824,16 @@ pcie0: pcie@1c00000 {
> pinctrl-0 = <&pcie0_default_state>;
>
> status = "disabled";
> +
> + pcie@0 {
> + device_type = "pci";
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + bus-range = <0x01 0xff>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + };
> };
>
> pcie0_phy: phy@1c06000 {
> @@ -1931,6 +1941,16 @@ pcie1: pcie@1c08000 {
> pinctrl-0 = <&pcie1_default_state>;
>
> status = "disabled";
> +
> + pcie@0 {
> + device_type = "pci";
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + bus-range = <0x01 0xff>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + };
> };
>
> pcie1_phy: phy@1c0e000 {
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 06/21] arm64: dts: qcom: sm8550: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (4 preceding siblings ...)
2024-02-21 3:41 ` [PATCH 05/21] arm64: dts: qcom: sm8450: " Manivannan Sadhasivam
@ 2024-02-21 3:41 ` Manivannan Sadhasivam
2024-02-21 12:46 ` neil.armstrong
2024-02-21 3:41 ` [PATCH 07/21] arm64: dts: qcom: sm8650: " Manivannan Sadhasivam
` (14 subsequent siblings)
20 siblings, 1 reply; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index ee1ba5a8c8fc..3ee11311885f 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1754,6 +1754,16 @@ pcie0: pcie@1c00000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_phy: phy@1c06000 {
@@ -1851,6 +1861,16 @@ pcie1: pcie@1c08000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_phy: phy@1c0e000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 06/21] arm64: dts: qcom: sm8550: Add PCIe bridge node
2024-02-21 3:41 ` [PATCH 06/21] arm64: dts: qcom: sm8550: " Manivannan Sadhasivam
@ 2024-02-21 12:46 ` neil.armstrong
0 siblings, 0 replies; 30+ messages in thread
From: neil.armstrong @ 2024-02-21 12:46 UTC (permalink / raw)
To: Manivannan Sadhasivam, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel
On 21/02/2024 04:41, Manivannan Sadhasivam wrote:
> On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
> for each controller instance. Hence, add a node to represent the bridge.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index ee1ba5a8c8fc..3ee11311885f 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1754,6 +1754,16 @@ pcie0: pcie@1c00000 {
> phy-names = "pciephy";
>
> status = "disabled";
> +
> + pcie@0 {
> + device_type = "pci";
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + bus-range = <0x01 0xff>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + };
> };
>
> pcie0_phy: phy@1c06000 {
> @@ -1851,6 +1861,16 @@ pcie1: pcie@1c08000 {
> phy-names = "pciephy";
>
> status = "disabled";
> +
> + pcie@0 {
> + device_type = "pci";
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + bus-range = <0x01 0xff>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + };
> };
>
> pcie1_phy: phy@1c0e000 {
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 07/21] arm64: dts: qcom: sm8650: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (5 preceding siblings ...)
2024-02-21 3:41 ` [PATCH 06/21] arm64: dts: qcom: sm8550: " Manivannan Sadhasivam
@ 2024-02-21 3:41 ` Manivannan Sadhasivam
2024-02-21 12:46 ` neil.armstrong
2024-02-21 3:41 ` [PATCH 08/21] arm64: dts: qcom: sa8775p: " Manivannan Sadhasivam
` (13 subsequent siblings)
20 siblings, 1 reply; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 2df77123a8c7..57a1ea84aa59 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2270,6 +2270,16 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
dma-coherent;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_phy: phy@1c06000 {
@@ -2379,6 +2389,16 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_phy: phy@1c0e000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 07/21] arm64: dts: qcom: sm8650: Add PCIe bridge node
2024-02-21 3:41 ` [PATCH 07/21] arm64: dts: qcom: sm8650: " Manivannan Sadhasivam
@ 2024-02-21 12:46 ` neil.armstrong
0 siblings, 0 replies; 30+ messages in thread
From: neil.armstrong @ 2024-02-21 12:46 UTC (permalink / raw)
To: Manivannan Sadhasivam, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel
On 21/02/2024 04:41, Manivannan Sadhasivam wrote:
> On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
> for each controller instance. Hence, add a node to represent the bridge.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index 2df77123a8c7..57a1ea84aa59 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -2270,6 +2270,16 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> dma-coherent;
>
> status = "disabled";
> +
> + pcie@0 {
> + device_type = "pci";
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + bus-range = <0x01 0xff>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + };
> };
>
> pcie0_phy: phy@1c06000 {
> @@ -2379,6 +2389,16 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>;
>
> status = "disabled";
> +
> + pcie@0 {
> + device_type = "pci";
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + bus-range = <0x01 0xff>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + };
> };
>
> pcie1_phy: phy@1c0e000 {
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 08/21] arm64: dts: qcom: sa8775p: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (6 preceding siblings ...)
2024-02-21 3:41 ` [PATCH 07/21] arm64: dts: qcom: sm8650: " Manivannan Sadhasivam
@ 2024-02-21 3:41 ` Manivannan Sadhasivam
2024-02-21 3:41 ` [PATCH 09/21] arm64: dts: qcom: sc8280xp: " Manivannan Sadhasivam
` (12 subsequent siblings)
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index a7eaca33d326..2d810d64b607 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3584,6 +3584,16 @@ pcie0: pcie@1c00000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_phy: phy@1c04000 {
@@ -3684,6 +3694,16 @@ pcie1: pcie@1c10000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_phy: phy@1c14000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 09/21] arm64: dts: qcom: sc8280xp: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (7 preceding siblings ...)
2024-02-21 3:41 ` [PATCH 08/21] arm64: dts: qcom: sa8775p: " Manivannan Sadhasivam
@ 2024-02-21 3:41 ` Manivannan Sadhasivam
2024-02-21 12:39 ` Konrad Dybcio
2024-02-21 3:41 ` [PATCH 10/21] arm64: dts: qcom: msm8998: " Manivannan Sadhasivam
` (11 subsequent siblings)
20 siblings, 1 reply; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
While at it, let's remove the bridge properties from board dts as they are
now redundant.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 8 -----
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 40 ++++++++++++++++++++++
2 files changed, 40 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index def3976bd5bb..f0a0115e08fa 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -733,14 +733,6 @@ &pcie4 {
status = "okay";
pcie@0 {
- device_type = "pci";
- reg = <0x0 0x0 0x0 0x0 0x0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- bus-range = <0x01 0xff>;
-
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index febf28356ff8..37d9e01d7e4e 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1779,6 +1779,16 @@ pcie4: pcie@1c00000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie4_phy: phy@1c06000 {
@@ -1877,6 +1887,16 @@ pcie3b: pcie@1c08000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie3b_phy: phy@1c0e000 {
@@ -1975,6 +1995,16 @@ pcie3a: pcie@1c10000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie3a_phy: phy@1c14000 {
@@ -2076,6 +2106,16 @@ pcie2b: pcie@1c18000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie2b_phy: phy@1c1e000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 09/21] arm64: dts: qcom: sc8280xp: Add PCIe bridge node
2024-02-21 3:41 ` [PATCH 09/21] arm64: dts: qcom: sc8280xp: " Manivannan Sadhasivam
@ 2024-02-21 12:39 ` Konrad Dybcio
2024-02-22 5:39 ` Manivannan Sadhasivam
0 siblings, 1 reply; 30+ messages in thread
From: Konrad Dybcio @ 2024-02-21 12:39 UTC (permalink / raw)
To: Manivannan Sadhasivam, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel
On 21.02.2024 04:41, Manivannan Sadhasivam wrote:
> On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
> for each controller instance. Hence, add a node to represent the bridge.
>
> While at it, let's remove the bridge properties from board dts as they are
> now redundant.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 8 -----
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 40 ++++++++++++++++++++++
> 2 files changed, 40 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> index def3976bd5bb..f0a0115e08fa 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> @@ -733,14 +733,6 @@ &pcie4 {
> status = "okay";
>
> pcie@0 {
> - device_type = "pci";
> - reg = <0x0 0x0 0x0 0x0 0x0>;
> - #address-cells = <3>;
> - #size-cells = <2>;
> - ranges;
> -
> - bus-range = <0x01 0xff>;
> -
> wifi@0 {
This doesn't seem right, pleas use a label
Konrad
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 09/21] arm64: dts: qcom: sc8280xp: Add PCIe bridge node
2024-02-21 12:39 ` Konrad Dybcio
@ 2024-02-22 5:39 ` Manivannan Sadhasivam
2024-03-18 3:37 ` Bjorn Andersson
0 siblings, 1 reply; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-22 5:39 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
cros-qcom-dts-watchers, linux-arm-msm, devicetree, linux-kernel
On Wed, Feb 21, 2024 at 01:39:01PM +0100, Konrad Dybcio wrote:
> On 21.02.2024 04:41, Manivannan Sadhasivam wrote:
> > On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
> > for each controller instance. Hence, add a node to represent the bridge.
> >
> > While at it, let's remove the bridge properties from board dts as they are
> > now redundant.
> >
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> > .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 8 -----
> > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 40 ++++++++++++++++++++++
> > 2 files changed, 40 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> > index def3976bd5bb..f0a0115e08fa 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> > @@ -733,14 +733,6 @@ &pcie4 {
> > status = "okay";
> >
> > pcie@0 {
> > - device_type = "pci";
> > - reg = <0x0 0x0 0x0 0x0 0x0>;
> > - #address-cells = <3>;
> > - #size-cells = <2>;
> > - ranges;
> > -
> > - bus-range = <0x01 0xff>;
> > -
> > wifi@0 {
>
> This doesn't seem right, pleas use a label
>
Why? A node label is useful if we want to reference it at the root level in
board dts, but here it is not.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 09/21] arm64: dts: qcom: sc8280xp: Add PCIe bridge node
2024-02-22 5:39 ` Manivannan Sadhasivam
@ 2024-03-18 3:37 ` Bjorn Andersson
2024-03-18 5:24 ` Manivannan Sadhasivam
0 siblings, 1 reply; 30+ messages in thread
From: Bjorn Andersson @ 2024-03-18 3:37 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
cros-qcom-dts-watchers, linux-arm-msm, devicetree, linux-kernel
On Thu, Feb 22, 2024 at 11:09:58AM +0530, Manivannan Sadhasivam wrote:
> On Wed, Feb 21, 2024 at 01:39:01PM +0100, Konrad Dybcio wrote:
> > On 21.02.2024 04:41, Manivannan Sadhasivam wrote:
> > > On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
> > > for each controller instance. Hence, add a node to represent the bridge.
> > >
> > > While at it, let's remove the bridge properties from board dts as they are
> > > now redundant.
> > >
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > ---
> > > .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 8 -----
> > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 40 ++++++++++++++++++++++
> > > 2 files changed, 40 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> > > index def3976bd5bb..f0a0115e08fa 100644
> > > --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> > > +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> > > @@ -733,14 +733,6 @@ &pcie4 {
> > > status = "okay";
> > >
> > > pcie@0 {
> > > - device_type = "pci";
> > > - reg = <0x0 0x0 0x0 0x0 0x0>;
> > > - #address-cells = <3>;
> > > - #size-cells = <2>;
> > > - ranges;
> > > -
> > > - bus-range = <0x01 0xff>;
> > > -
> > > wifi@0 {
> >
> > This doesn't seem right, pleas use a label
> >
>
> Why? A node label is useful if we want to reference it at the root level in
> board dts, but here it is not.
>
Giving the bridge a label and then adding wifi@0 as a child using that
label in the dts is pretty much how we do for everything else.
I find this over-flattening hard to follow, but relying on child node
names when extending the structure or adding properties have bitten us
many times in the past.
As such, I think the desired result in the dts should be:
&pcie4 {
status = "okay";
};
&pcie4_bridge {
wifi@0 {
...
};
};
Regards,
Bjorn
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 09/21] arm64: dts: qcom: sc8280xp: Add PCIe bridge node
2024-03-18 3:37 ` Bjorn Andersson
@ 2024-03-18 5:24 ` Manivannan Sadhasivam
0 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-03-18 5:24 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
cros-qcom-dts-watchers, linux-arm-msm, devicetree, linux-kernel
On Sun, Mar 17, 2024 at 10:37:15PM -0500, Bjorn Andersson wrote:
> On Thu, Feb 22, 2024 at 11:09:58AM +0530, Manivannan Sadhasivam wrote:
> > On Wed, Feb 21, 2024 at 01:39:01PM +0100, Konrad Dybcio wrote:
> > > On 21.02.2024 04:41, Manivannan Sadhasivam wrote:
> > > > On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
> > > > for each controller instance. Hence, add a node to represent the bridge.
> > > >
> > > > While at it, let's remove the bridge properties from board dts as they are
> > > > now redundant.
> > > >
> > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > > ---
> > > > .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 8 -----
> > > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 40 ++++++++++++++++++++++
> > > > 2 files changed, 40 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> > > > index def3976bd5bb..f0a0115e08fa 100644
> > > > --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> > > > +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> > > > @@ -733,14 +733,6 @@ &pcie4 {
> > > > status = "okay";
> > > >
> > > > pcie@0 {
> > > > - device_type = "pci";
> > > > - reg = <0x0 0x0 0x0 0x0 0x0>;
> > > > - #address-cells = <3>;
> > > > - #size-cells = <2>;
> > > > - ranges;
> > > > -
> > > > - bus-range = <0x01 0xff>;
> > > > -
> > > > wifi@0 {
> > >
> > > This doesn't seem right, pleas use a label
> > >
> >
> > Why? A node label is useful if we want to reference it at the root level in
> > board dts, but here it is not.
> >
>
> Giving the bridge a label and then adding wifi@0 as a child using that
> label in the dts is pretty much how we do for everything else.
>
> I find this over-flattening hard to follow, but relying on child node
> names when extending the structure or adding properties have bitten us
> many times in the past.
>
> As such, I think the desired result in the dts should be:
>
> &pcie4 {
> status = "okay";
> };
>
> &pcie4_bridge {
> wifi@0 {
> ...
> };
> };
>
Ok. Will change it in next version. I'm also waiting to conclude on representing
the PERST# and WAKE# properties properly in the schema [1]. Once that gets
finalized, I'll respin v2.
- Mani
[1] https://github.com/devicetree-org/dt-schema/pull/126
> Regards,
> Bjorn
>
> > - Mani
> >
> > --
> > மணிவண்ணன் சதாசிவம்
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 10/21] arm64: dts: qcom: msm8998: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (8 preceding siblings ...)
2024-02-21 3:41 ` [PATCH 09/21] arm64: dts: qcom: sc8280xp: " Manivannan Sadhasivam
@ 2024-02-21 3:41 ` Manivannan Sadhasivam
2024-02-21 3:41 ` [PATCH 11/21] arm64: dts: qcom: sc7280: " Manivannan Sadhasivam
` (10 subsequent siblings)
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 2793cc22d381..5d85757628d0 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -972,6 +972,16 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie_phy: phy@1c06000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 11/21] arm64: dts: qcom: sc7280: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (9 preceding siblings ...)
2024-02-21 3:41 ` [PATCH 10/21] arm64: dts: qcom: msm8998: " Manivannan Sadhasivam
@ 2024-02-21 3:41 ` Manivannan Sadhasivam
2024-02-21 3:41 ` [PATCH 12/21] arm64: dts: qcom: qcs404: " Manivannan Sadhasivam
` (9 subsequent siblings)
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 83b5b76ba179..3b52d467dc8d 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2235,6 +2235,16 @@ pcie1: pcie@1c08000 {
<0x100 &apps_smmu 0x1c81 0x1>;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_phy: phy@1c0e000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 12/21] arm64: dts: qcom: qcs404: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (10 preceding siblings ...)
2024-02-21 3:41 ` [PATCH 11/21] arm64: dts: qcom: sc7280: " Manivannan Sadhasivam
@ 2024-02-21 3:41 ` Manivannan Sadhasivam
2024-02-21 3:41 ` [PATCH 13/21] arm64: dts: qcom: sc8180x: " Manivannan Sadhasivam
` (8 subsequent siblings)
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 2f2eeaf2e945..80308157fb03 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -1500,6 +1500,16 @@ pcie: pcie@10000000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 13/21] arm64: dts: qcom: sc8180x: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (11 preceding siblings ...)
2024-02-21 3:41 ` [PATCH 12/21] arm64: dts: qcom: qcs404: " Manivannan Sadhasivam
@ 2024-02-21 3:41 ` Manivannan Sadhasivam
2024-02-21 3:42 ` [PATCH 14/21] arm64: dts: qcom: msm8996: " Manivannan Sadhasivam
` (7 subsequent siblings)
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 40 +++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 0430d99091e3..a6134f454e53 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -1754,6 +1754,16 @@ pcie0: pcie@1c00000 {
dma-coherent;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_phy: phy@1c06000 {
@@ -1851,6 +1861,16 @@ pcie3: pcie@1c08000 {
dma-coherent;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie3_phy: phy@1c0c000 {
@@ -1949,6 +1969,16 @@ pcie1: pcie@1c10000 {
dma-coherent;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_phy: phy@1c16000 {
@@ -2047,6 +2077,16 @@ pcie2: pcie@1c18000 {
dma-coherent;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie2_phy: phy@1c1c000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 14/21] arm64: dts: qcom: msm8996: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (12 preceding siblings ...)
2024-02-21 3:41 ` [PATCH 13/21] arm64: dts: qcom: sc8180x: " Manivannan Sadhasivam
@ 2024-02-21 3:42 ` Manivannan Sadhasivam
2024-02-21 3:42 ` [PATCH 15/21] arm64: dts: qcom: ipq8074: " Manivannan Sadhasivam
` (6 subsequent siblings)
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:42 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 8d41ed261adf..cd28b368ebb6 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1956,6 +1956,16 @@ pcie0: pcie@600000 {
"cfg",
"bus_master",
"bus_slave";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1: pcie@608000 {
@@ -2009,6 +2019,16 @@ pcie1: pcie@608000 {
"cfg",
"bus_master",
"bus_slave";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie2: pcie@610000 {
@@ -2059,6 +2079,16 @@ pcie2: pcie@610000 {
"cfg",
"bus_master",
"bus_slave";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 15/21] arm64: dts: qcom: ipq8074: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (13 preceding siblings ...)
2024-02-21 3:42 ` [PATCH 14/21] arm64: dts: qcom: msm8996: " Manivannan Sadhasivam
@ 2024-02-21 3:42 ` Manivannan Sadhasivam
2024-02-21 3:42 ` [PATCH 16/21] arm64: dts: qcom: ipq6018: " Manivannan Sadhasivam
` (5 subsequent siblings)
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:42 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index cf295bed3299..ae1677362421 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -848,6 +848,16 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
"ahb",
"axi_m_sticky";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0: pcie@20000000 {
@@ -913,6 +923,16 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
"axi_m_sticky",
"axi_s_sticky";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 16/21] arm64: dts: qcom: ipq6018: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (14 preceding siblings ...)
2024-02-21 3:42 ` [PATCH 15/21] arm64: dts: qcom: ipq8074: " Manivannan Sadhasivam
@ 2024-02-21 3:42 ` Manivannan Sadhasivam
2024-02-21 3:42 ` [PATCH 17/21] ARM: dts: qcom: ipq8064: " Manivannan Sadhasivam
` (4 subsequent siblings)
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:42 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 5e1277fea725..a6ace7789815 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -864,6 +864,16 @@ pcie0: pcie@20000000 {
"axi_s_sticky";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 17/21] ARM: dts: qcom: ipq8064: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (15 preceding siblings ...)
2024-02-21 3:42 ` [PATCH 16/21] arm64: dts: qcom: ipq6018: " Manivannan Sadhasivam
@ 2024-02-21 3:42 ` Manivannan Sadhasivam
2024-02-21 3:42 ` [PATCH 18/21] ARM: dts: qcom: ipq4019: " Manivannan Sadhasivam
` (3 subsequent siblings)
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:42 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
index 6a7f4dd0f775..98448ea6ffca 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
@@ -1125,6 +1125,16 @@ pcie0: pcie@1b500000 {
status = "disabled";
perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1: pcie@1b700000 {
@@ -1176,6 +1186,16 @@ pcie1: pcie@1b700000 {
status = "disabled";
perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie2: pcie@1b900000 {
@@ -1227,6 +1247,16 @@ pcie2: pcie@1b900000 {
status = "disabled";
perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
qsgmii_csr: syscon@1bb00000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 18/21] ARM: dts: qcom: ipq4019: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (16 preceding siblings ...)
2024-02-21 3:42 ` [PATCH 17/21] ARM: dts: qcom: ipq8064: " Manivannan Sadhasivam
@ 2024-02-21 3:42 ` Manivannan Sadhasivam
2024-02-21 3:42 ` [PATCH 19/21] ARM: dts: qcom: apq8064: " Manivannan Sadhasivam
` (2 subsequent siblings)
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:42 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
index f989bd741cd1..03bd421a2ce7 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
@@ -475,6 +475,16 @@ pcie0: pcie@40000000 {
"phy_ahb";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
qpic_bam: dma-controller@7984000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 19/21] ARM: dts: qcom: apq8064: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (17 preceding siblings ...)
2024-02-21 3:42 ` [PATCH 18/21] ARM: dts: qcom: ipq4019: " Manivannan Sadhasivam
@ 2024-02-21 3:42 ` Manivannan Sadhasivam
2024-02-21 3:42 ` [PATCH 20/21] ARM: dts: qcom: sdx55: " Manivannan Sadhasivam
2024-02-21 3:42 ` [PATCH 21/21] arm64: dts: qcom: sm8650: Use "pcie" as the node name instead of "pci" Manivannan Sadhasivam
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:42 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
index 3faf57035d54..1ebd6cef4057 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
@@ -1318,6 +1318,16 @@ pcie: pcie@1b500000 {
<&gcc PCIE_PHY_RESET>;
reset-names = "axi", "ahb", "por", "pci", "phy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
hdmi: hdmi-tx@4a00000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 20/21] ARM: dts: qcom: sdx55: Add PCIe bridge node
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (18 preceding siblings ...)
2024-02-21 3:42 ` [PATCH 19/21] ARM: dts: qcom: apq8064: " Manivannan Sadhasivam
@ 2024-02-21 3:42 ` Manivannan Sadhasivam
2024-02-21 3:42 ` [PATCH 21/21] arm64: dts: qcom: sm8650: Use "pcie" as the node name instead of "pci" Manivannan Sadhasivam
20 siblings, 0 replies; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:42 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
index 2045fc779f88..053dac097c70 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
@@ -378,6 +378,16 @@ pcie_rc: pcie@1c00000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie_ep: pcie-ep@1c00000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 21/21] arm64: dts: qcom: sm8650: Use "pcie" as the node name instead of "pci"
2024-02-21 3:41 [PATCH 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
` (19 preceding siblings ...)
2024-02-21 3:42 ` [PATCH 20/21] ARM: dts: qcom: sdx55: " Manivannan Sadhasivam
@ 2024-02-21 3:42 ` Manivannan Sadhasivam
2024-02-21 12:39 ` Konrad Dybcio
20 siblings, 1 reply; 30+ messages in thread
From: Manivannan Sadhasivam @ 2024-02-21 3:42 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel, Manivannan Sadhasivam
Qcom SoCs doesn't support legacy PCI, but only PCIe. So use the correct
node name for the controller instances.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 57a1ea84aa59..1b226499175a 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2203,7 +2203,7 @@ rng: rng@10c3000 {
reg = <0 0x010c3000 0 0x1000>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
reg = <0 0x01c00000 0 0x3000>,
@@ -2313,7 +2313,7 @@ pcie0_phy: phy@1c06000 {
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
device_type = "pci";
compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
reg = <0 0x01c08000 0 0x3000>,
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 21/21] arm64: dts: qcom: sm8650: Use "pcie" as the node name instead of "pci"
2024-02-21 3:42 ` [PATCH 21/21] arm64: dts: qcom: sm8650: Use "pcie" as the node name instead of "pci" Manivannan Sadhasivam
@ 2024-02-21 12:39 ` Konrad Dybcio
0 siblings, 0 replies; 30+ messages in thread
From: Konrad Dybcio @ 2024-02-21 12:39 UTC (permalink / raw)
To: Manivannan Sadhasivam, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, cros-qcom-dts-watchers
Cc: linux-arm-msm, devicetree, linux-kernel
On 21.02.2024 04:42, Manivannan Sadhasivam wrote:
> Qcom SoCs doesn't support legacy PCI, but only PCIe. So use the correct
> node name for the controller instances.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply [flat|nested] 30+ messages in thread