From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF706612FF; Mon, 4 Mar 2024 17:49:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709574569; cv=none; b=msNI/5JUmq0dMi/+ZcOknckw7Kazj3CMWP6crcFwem6tAB/7SsykTOc8Oq9bjSHaNf0rp+xn29tIwtbY8uO6I9rqNOg3vq92OhVCn5APpb0T9dCOoyM5q07PovaVPEoRMLqTN1SUhwipC5xKvVIN3ncomlUtoaxAllUjkEEWH0A= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709574569; c=relaxed/simple; bh=yd3DG/OWoHxPS1GFw4PLIDi3ucW798a2Y8kNvy9b8wk=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=b5tEOPZSq/Iy1cXkFcPVa4ofS3JUozJUvrnYjKd/zCRodxcUXY5nZMq2OP0lkuxWCRHVvmqcrYn/ME0FmMHbGPImeyQBx9N/FAEUQRmE7dP8xsug2Tk+eHdGhuryIk/z0RWi+MwHqNgeeEoLtfhhb1ltgepTo/580XsHej8VGGw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uF52TUP0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uF52TUP0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06876C43390; Mon, 4 Mar 2024 17:49:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1709574569; bh=yd3DG/OWoHxPS1GFw4PLIDi3ucW798a2Y8kNvy9b8wk=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=uF52TUP0tpTMiUhBlzWL8cf+qju3fYNTFrzc8ikHGCPuqW33VmTL0e4XtuxizutKB sQLWSspT+OHrnjR2jXFPifQeE1EjuncmhFTM9IBrDxBA7nLz2P3MAmY7eBDb+Lwac7 qFHADkYoMgg8ZxGOXo3MQ/Akt6h4NizrQzoIyS6IHIAbyXzvIWJpoN5EBfhGOn+ebg DM74vlR/O6OIl//4DjAPQFPhpWqOpSikD57muDEqtgNa43jeGKXmR/BgztQcjAJqhb Qo4lMMPoO9kLPIvMI3+DYuaGxiJO6CC3Z2XsRiZ3l0ZO92JQ1xxD0gG18kI4kbbIzi +OY1tojEhPf0A== Date: Mon, 4 Mar 2024 23:19:17 +0530 From: Manivannan Sadhasivam To: Krishna chaitanya chundru Cc: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Rob Herring , Johan Hovold , Brian Masney , Georgi Djakov , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vireshk@kernel.org, quic_vbadigan@quicinc.com, quic_skananth@quicinc.com, quic_nitegupt@quicinc.com, quic_parass@quicinc.com Subject: Re: [PATCH v8 5/7] arm64: dts: qcom: sm8450: Add opp table support to PCIe Message-ID: <20240304174917.GC31079@thinkpad> References: <20240302-opp_support-v8-0-158285b86b10@quicinc.com> <20240302-opp_support-v8-5-158285b86b10@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240302-opp_support-v8-5-158285b86b10@quicinc.com> On Sat, Mar 02, 2024 at 09:29:59AM +0530, Krishna chaitanya chundru wrote: > PCIe needs to choose the appropriate performance state of RPMH power > domain and interconnect bandwidth based up on the PCIe gen speed. > > Add the OPP table support to specify RPMH performance states and > interconnect peak bandwidth. > > Signed-off-by: Krishna chaitanya chundru > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 74 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 74 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 6b1d2e0d9d14..662f2129f20d 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -1827,7 +1827,32 @@ pcie0: pcie@1c00000 { > pinctrl-names = "default"; > pinctrl-0 = <&pcie0_default_state>; > > + operating-points-v2 = <&pcie0_opp_table>; > + > status = "disabled"; > + > + pcie0_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-2500000 { Add the comments that you added below. > + opp-hz = /bits/ 64 <2500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + opp-peak-kBps = <250000 1>; Isn't the peak bw should be greater that the avg bw? Atleast in upstream we follow that pattern. - Mani > + }; > + > + opp-5000000 { > + opp-hz = /bits/ 64 <5000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + opp-peak-kBps = <500000 1>; > + }; > + > + opp-8000000 { > + opp-hz = /bits/ 64 <8000000>; > + required-opps = <&rpmhpd_opp_nom>; > + opp-peak-kBps = <984500 1>; > + }; > + }; > + > }; > > pcie0_phy: phy@1c06000 { > @@ -1938,7 +1963,56 @@ pcie1: pcie@1c08000 { > pinctrl-names = "default"; > pinctrl-0 = <&pcie1_default_state>; > > + operating-points-v2 = <&pcie1_opp_table>; > + > status = "disabled"; > + > + pcie1_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + /* GEN 1x1 */ > + opp-2500000 { > + opp-hz = /bits/ 64 <2500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + opp-peak-kBps = <250000 1>; > + }; > + > + /* GEN 1x2 GEN 2x1 */ > + opp-5000000 { > + opp-hz = /bits/ 64 <5000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + opp-peak-kBps = <500000 1>; > + }; > + > + /* GEN 2x2 */ > + opp-10000000 { > + opp-hz = /bits/ 64 <10000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + opp-peak-kBps = <1000000 1>; > + }; > + > + /* GEN 3x1 */ > + opp-8000000 { > + opp-hz = /bits/ 64 <8000000>; > + required-opps = <&rpmhpd_opp_nom>; > + opp-peak-kBps = <984500 1>; > + }; > + > + /* GEN 3x2 GEN 4x1 */ > + opp-16000000 { > + opp-hz = /bits/ 64 <16000000>; > + required-opps = <&rpmhpd_opp_nom>; > + opp-peak-kBps = <1969000 1>; > + }; > + > + /* GEN 4x2 */ > + opp-32000000 { > + opp-hz = /bits/ 64 <32000000>; > + required-opps = <&rpmhpd_opp_nom>; > + opp-peak-kBps = <3938000 1>; > + }; > + }; > + > }; > > pcie1_phy: phy@1c0e000 { > > -- > 2.42.0 > -- மணிவண்ணன் சதாசிவம்