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charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240321-pcie-qcom-bridge-dts-v2-10-1eb790c53e43@linaro.org> References: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> In-Reply-To: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Rob Herring Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=963; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=IZvlsFRd/io8/lLci8Xst/yB1RdYXUKGx4G/k54i+hs=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl/BcLJsmmf1/3whfwiEfF7DlWSN0HkR8ykSM8d 8Js69Ai596JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZfwXCwAKCRBVnxHm/pHO 9SD1CACkmq967TLg2byz+bPC1qRq5tQ5qN/x+8wAbyH2Qau2L7reKq8mbk864MkENvJK2czjMjZ 7IlV1b9CepvCAhkU0NvpYirVHypcwafP0gn2LJ34/iIBvUXZzirAQdK5tpJV4vbmXoyOcDV21fv YPmcTz5SqqRuUe1ZPIIj2OILkzhJOp9ZAxpIrNa+98F2r8OfQyjR6QPuxOy3eXDzbcCPpdnr3QE hFHOeGO+R8rjhvJhcurR6pS6C2sgS8YxWu/lOBs8lJxbM112uUt1pGm8HRDZj72vdQfUHiKE8my 0385HqAvEbij53Hp3O3juZzObI1ahRA+bq3AQpB43EtqnLvv X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 4dfe2d09ac28..d795b2bbe133 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -972,6 +972,16 @@ pcie0: pcie@1c00000 { power-domains = <&gcc PCIE_0_GDSC>; iommu-map = <0x100 &anoc1_smmu 0x1480 1>; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie_phy: phy@1c06000 { -- 2.25.1