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charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240321-pcie-qcom-bridge-dts-v2-5-1eb790c53e43@linaro.org> References: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> In-Reply-To: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Rob Herring Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1306; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=BP3xpp0v4tnL/9I1fNzpSMYSMwKKsX1sNJSehWncIwY=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl/BcK+PRb1g48X4N+HBsPz98fCwxJJpV1gchQM N4EuzgM896JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZfwXCgAKCRBVnxHm/pHO 9X7eB/0Q5ajmD9X1C3Z5xChBXdgcY4QYTzjaKHXD8Mww9L3OyaWYeMLGuHnJimU7PsyNAhXUwqi XMvyMdDPOWM2IT2VavorgIH4oRYQPdUt8Cs4LmyTMynXsBxkdzepsltBY4fSndcYWqZYeg+RPIO wuzrxoM6YEYndf+CRDtcaL8xdSDoUCQUJPPeKOgIaPwbTucjLNPizf9EHgFaJA6ek4hYs+QbOz/ Pm7ar/l1DjdHZ1d2tfbYE3bWwYgowOVZLcBXsmxvrlm3WnbijQCpHuCfwamU/uPl3BSpdAtxqIR V3QkibGvMF06jH1RFezsZXo/gW5DZ5yiiFhxXnAA0vHcCuK5 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Reviewed-by: Neil Armstrong Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index b86be34a912b..b42e44b922de 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1850,6 +1850,16 @@ pcie0: pcie@1c00000 { pinctrl-0 = <&pcie0_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1971,6 +1981,16 @@ pcie1: pcie@1c08000 { pinctrl-0 = <&pcie1_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { -- 2.25.1