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charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240321-pcie-qcom-bridge-dts-v2-6-1eb790c53e43@linaro.org> References: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> In-Reply-To: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Rob Herring Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1280; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=5GcAJHlBvKdEoubmGeSAXTJD4cDVK4cWaitoqpJbgQY=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl/BcKdnv9eU+5NjUZRC2zsEE6+iJujn3ML13Tb OUIoeLu57GJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZfwXCgAKCRBVnxHm/pHO 9RObB/0V6WSbb9d/QuL/IN/igbT/U8ZVi1TtULvhzAA19in1yQ0fF4lafvGCOmIQVgqmIZEFUQf jVc1UIGQLl7Z8nQyazTRu2bGDscoNcLvQBie5ijCUVnAUlA13OF4xYYf7dkIkoW7b2/TMZZgxPR jhe1yM1n35EOKf6+UD4eVfbP/1jFFXLoUrfAW2Oq3OORJvCRgt8ooHasDNKyu9GbcazPrKg/lIt pDip4FZ0aDDsnvfyJxGz2Pl5Myr23sM3pj4qh5YDdAWbqk8HXVU7VhFEu13m1sgUnHb2RNjiFy3 kFYcA0IpJ+9LBIxPDS87fGvAIqn/+abQ47HQNEXQ5PLvthtY X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Reviewed-by: Neil Armstrong Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 3904348075f6..760b6a6cb59c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1770,6 +1770,16 @@ pcie0: pcie@1c00000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1883,6 +1893,16 @@ pcie1: pcie@1c08000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { -- 2.25.1