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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id s16-20020a05600c45d000b00413f4cb62e1sm2291207wmo.23.2024.03.22.01.09.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 01:09:50 -0700 (PDT) Date: Fri, 22 Mar 2024 09:09:49 +0100 From: Andrew Jones To: Deepak Gupta Cc: Samuel Holland , Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, tech-j-ext@lists.risc-v.org, Conor Dooley , kasan-dev@googlegroups.com, Evgenii Stepanov , Krzysztof Kozlowski , Rob Herring , Guo Ren , Heiko Stuebner , Paul Walmsley Subject: Re: [RISC-V] [tech-j-ext] [RFC PATCH 5/9] riscv: Split per-CPU and per-thread envcfg bits Message-ID: <20240322-3c32873c4021477383a15f7d@orel> References: <20240319215915.832127-1-samuel.holland@sifive.com> <20240319215915.832127-6-samuel.holland@sifive.com> <40ab1ce5-8700-4a63-b182-1e864f6c9225@sifive.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Mar 19, 2024 at 09:39:52PM -0700, Deepak Gupta wrote: ... > I am not sure of the practicality of this heterogeneity for Zicboz and > for that matter any of the upcoming > features that'll be enabled via senvcfg (control flow integrity, > pointer masking, etc). > > As an example if cache zeroing instructions are used by app binary, I > expect it to be used in following > manner > > - Explicitly inserting cbo.zero by application developer > - Some compiler flag which ensures that structures larger than cache > line gets zeroed by cbo.zero > > In either of the cases, the developer is not expecting to target it to > a specific hart on SoC and instead expect it to work. > There might be libraries (installed via sudo apt get) with cache zero > support in them which may run in different address spaces. > Should the library be aware of the CPU on which it's running. Now > whoever is running these binaries should be aware which CPUs > they get assigned to in order to avoid faults? > > That seems excessive, doesn't it? > It might be safe to assume extensions like Zicboz will be on all harts if any, but I wouldn't expect all extensions in the future to be present on all available harts. For example, some Arm big.LITTLE boards only have virt extensions on big CPUs. When a VMM wants to launch a guest it must be aware of which CPUs it will use for the VCPU threads. For riscv, we have the which-cpus variant of the hwprobe syscall to try and make this type of thing easier to manage, but I agree it will still be a pain for software since it will need to make that query and then set its affinity, which is something it hasn't needed to do before. Thanks, drew