From: Rob Herring <robh@kernel.org>
To: Dmitry Rokosov <ddrokosov@salutedevices.com>
Cc: neil.armstrong@linaro.org, jbrunet@baylibre.com,
mturquette@baylibre.com, sboyd@kernel.org,
krzysztof.kozlowski+dt@linaro.org, khilman@baylibre.com,
martin.blumenstingl@googlemail.com, kernel@salutedevices.com,
rockosov@gmail.com, linux-amlogic@lists.infradead.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 3/6] dt-bindings: clock: meson: a1: peripherals: support sys_pll_div16 input
Date: Mon, 1 Apr 2024 09:21:36 -0500 [thread overview]
Message-ID: <20240401142136.GA559114-robh@kernel.org> (raw)
In-Reply-To: <20240329205904.25002-4-ddrokosov@salutedevices.com>
On Fri, Mar 29, 2024 at 11:58:43PM +0300, Dmitry Rokosov wrote:
> The 'sys_pll_div16' input clock is used as one of the sources for the
> GEN clock.
>
> Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
> ---
> .../bindings/clock/amlogic,a1-peripherals-clkc.yaml | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml
> index 6d84cee1bd75..f6668991ff1f 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml
> @@ -29,6 +29,7 @@ properties:
> - description: input fixed pll div5
> - description: input fixed pll div7
> - description: input hifi pll
> + - description: input sys pll div16
> - description: input oscillator (usually at 24MHz)
>
> clock-names:
> @@ -38,6 +39,7 @@ properties:
> - const: fclk_div5
> - const: fclk_div7
> - const: hifi_pll
> + - const: sys_pll_div16
> - const: xtal
And adding an entry in the middle is also an ABI break. New entries go
on the end (and should be optional).
next prev parent reply other threads:[~2024-04-01 14:21 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-29 20:58 [PATCH v1 0/6] clk: meson: introduce Amlogic A1 SoC Family CPU clock controller driver Dmitry Rokosov
2024-03-29 20:58 ` [PATCH v1 1/6] dt-bindings: clock: meson: a1: pll: introduce new syspll bindings Dmitry Rokosov
2024-04-01 14:20 ` Rob Herring
2024-04-01 17:22 ` Dmitry Rokosov
2024-03-29 20:58 ` [PATCH v1 2/6] clk: meson: a1: pll: support 'syspll' general-purpose PLL for CPU clock Dmitry Rokosov
2024-04-02 9:00 ` Jerome Brunet
2024-04-02 12:15 ` Dmitry Rokosov
2024-04-02 14:27 ` Jerome Brunet
2024-04-02 15:00 ` Dmitry Rokosov
2024-03-29 20:58 ` [PATCH v1 3/6] dt-bindings: clock: meson: a1: peripherals: support sys_pll_div16 input Dmitry Rokosov
2024-04-01 14:21 ` Rob Herring [this message]
2024-04-01 17:19 ` Dmitry Rokosov
2024-03-29 20:58 ` [PATCH v1 4/6] clk: meson: a1: peripherals: support 'sys_pll_div16' clock as GEN input Dmitry Rokosov
2024-03-29 20:58 ` [PATCH v1 5/6] dt-bindings: clock: meson: add A1 CPU clock controller bindings Dmitry Rokosov
2024-04-01 14:57 ` Rob Herring
2024-03-29 20:58 ` [PATCH v1 6/6] clk: meson: a1: add Amlogic A1 CPU clock controller driver Dmitry Rokosov
2024-03-31 21:40 ` Martin Blumenstingl
2024-04-01 17:12 ` Dmitry Rokosov
2024-04-02 9:27 ` Jerome Brunet
2024-04-02 11:43 ` Dmitry Rokosov
2024-04-02 9:35 ` Jerome Brunet
2024-04-02 11:05 ` Dmitry Rokosov
2024-04-02 14:11 ` Jerome Brunet
2024-04-02 16:11 ` Dmitry Rokosov
2024-04-02 16:17 ` Jerome Brunet
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