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From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Bjorn Andersson <andersson@kernel.org>,
	Rob Clark <robdclark@gmail.com>,
	 Abhinav Kumar <quic_abhinavk@quicinc.com>,
	 Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	Sean Paul <sean@poorly.run>,
	 Marijn Suijten <marijn.suijten@somainline.org>,
	 David Airlie <airlied@gmail.com>,
	Daniel Vetter <daniel@ffwll.ch>,  Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	 dri-devel@lists.freedesktop.org,
	freedreno@lists.freedesktop.org,  devicetree@vger.kernel.org,
	Neil Armstrong <neil.armstrong@linaro.org>,
	 Konrad Dybcio <konrad.dybcio@linaro.org>
Subject: [PATCH v2 2/7] soc: qcom: smem: Add a feature code getter
Date: Wed, 17 Apr 2024 22:02:54 +0200	[thread overview]
Message-ID: <20240404-topic-smem_speedbin-v2-2-c84f820b7e5b@linaro.org> (raw)
In-Reply-To: <20240404-topic-smem_speedbin-v2-0-c84f820b7e5b@linaro.org>

Recent (SM8550+ ish) Qualcomm SoCs have a new mechanism for precisely
identifying the specific SKU and the precise speed bin (in the general
meaning of this word, anyway): a pair of values called Product Code
and Feature Code.

Based on this information, we can deduce the available frequencies for
things such as Adreno. In the case of Adreno specifically, Pcode is
useless for non-prototype SoCs.

Introduce a getter for the feature code and export it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/soc/qcom/smem.c          | 33 +++++++++++++++++++++++++++++++++
 include/linux/soc/qcom/smem.h    |  1 +
 include/linux/soc/qcom/socinfo.h | 26 ++++++++++++++++++++++++++
 3 files changed, 60 insertions(+)

diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c
index 7191fa0c087f..29e708789eec 100644
--- a/drivers/soc/qcom/smem.c
+++ b/drivers/soc/qcom/smem.c
@@ -795,6 +795,39 @@ int qcom_smem_get_soc_id(u32 *id)
 }
 EXPORT_SYMBOL_GPL(qcom_smem_get_soc_id);
 
+/**
+ * qcom_smem_get_feature_code() - return the feature code
+ * @code: On success, return the feature code here.
+ *
+ * Look up the feature code identifier from SMEM and return it.
+ *
+ * Return: 0 on success, negative errno on failure.
+ */
+int qcom_smem_get_feature_code(u32 *code)
+{
+	struct socinfo *info;
+	u32 raw_code;
+
+	info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL);
+	if (IS_ERR(info))
+		return PTR_ERR(info);
+
+	/* This only makes sense for socinfo >= 16 */
+	if (__le32_to_cpu(info->fmt) < SOCINFO_VERSION(0, 16))
+		return -EOPNOTSUPP;
+
+	raw_code = __le32_to_cpu(info->feature_code);
+
+	/* Ensure the value makes sense */
+	if (raw_code >= SOCINFO_FC_INT_MAX)
+		raw_code = SOCINFO_FC_UNKNOWN;
+
+	*code = raw_code;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(qcom_smem_get_feature_code);
+
 static int qcom_smem_get_sbl_version(struct qcom_smem *smem)
 {
 	struct smem_header *header;
diff --git a/include/linux/soc/qcom/smem.h b/include/linux/soc/qcom/smem.h
index a36a3b9d4929..0943bf419e11 100644
--- a/include/linux/soc/qcom/smem.h
+++ b/include/linux/soc/qcom/smem.h
@@ -13,5 +13,6 @@ int qcom_smem_get_free_space(unsigned host);
 phys_addr_t qcom_smem_virt_to_phys(void *p);
 
 int qcom_smem_get_soc_id(u32 *id);
+int qcom_smem_get_feature_code(u32 *code);
 
 #endif
diff --git a/include/linux/soc/qcom/socinfo.h b/include/linux/soc/qcom/socinfo.h
index 10e0a4c287f4..52439f48428f 100644
--- a/include/linux/soc/qcom/socinfo.h
+++ b/include/linux/soc/qcom/socinfo.h
@@ -3,6 +3,8 @@
 #ifndef __QCOM_SOCINFO_H__
 #define __QCOM_SOCINFO_H__
 
+#include <linux/types.h>
+
 /*
  * SMEM item id, used to acquire handles to respective
  * SMEM region.
@@ -82,4 +84,28 @@ struct socinfo {
 	__le32 boot_core;
 };
 
+/* Internal feature codes */
+enum qcom_socinfo_feature_code {
+	/* External feature codes */
+	SOCINFO_FC_UNKNOWN = 0x0,
+	SOCINFO_FC_AA,
+	SOCINFO_FC_AB,
+	SOCINFO_FC_AC,
+	SOCINFO_FC_AD,
+	SOCINFO_FC_AE,
+	SOCINFO_FC_AF,
+	SOCINFO_FC_AG,
+	SOCINFO_FC_AH,
+};
+
+/* Internal feature codes */
+/* Valid values: 0 <= n <= 0xf */
+#define SOCINFO_FC_Yn(n)		(0xf1 + n)
+#define SOCINFO_FC_INT_MAX		SOCINFO_FC_Yn(0x10)
+
+/* Product codes */
+#define SOCINFO_PC_UNKNOWN		0
+#define SOCINFO_PCn(n)			(n + 1)
+#define SOCINFO_PC_RESERVE		(BIT(31) - 1)
+
 #endif

-- 
2.44.0


  parent reply	other threads:[~2024-04-17 20:03 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-17 20:02 [PATCH v2 0/7] Add SMEM-based speedbin matching Konrad Dybcio
2024-04-17 20:02 ` [PATCH v2 1/7] soc: qcom: Move some socinfo defines to the header Konrad Dybcio
2024-04-17 20:02 ` Konrad Dybcio [this message]
2024-04-17 23:39   ` [PATCH v2 2/7] soc: qcom: smem: Add a feature code getter Dmitry Baryshkov
2024-04-18  9:53     ` Konrad Dybcio
2024-04-18 11:06       ` Dmitry Baryshkov
2024-05-28 21:06   ` Bjorn Andersson
2024-04-17 20:02 ` [PATCH v2 3/7] drm/msm/adreno: Implement SMEM-based speed bin Konrad Dybcio
2024-04-17 23:43   ` Dmitry Baryshkov
2024-04-18  9:51     ` Konrad Dybcio
2024-04-18 11:07       ` Dmitry Baryshkov
2024-04-18 11:31         ` Konrad Dybcio
2024-04-18 11:48           ` Dmitry Baryshkov
2024-04-17 20:02 ` [PATCH v2 4/7] drm/msm/adreno: Add speedbin data for SM8550 / A740 Konrad Dybcio
2024-04-17 23:44   ` Dmitry Baryshkov
2024-04-17 20:02 ` [PATCH v2 5/7] drm/msm/adreno: Define A530 speed bins explicitly Konrad Dybcio
2024-04-17 23:44   ` Dmitry Baryshkov
2024-04-17 20:02 ` [PATCH v2 6/7] drm/msm/adreno: Redo the speedbin assignment Konrad Dybcio
2024-04-17 23:49   ` Dmitry Baryshkov
2024-04-18  9:57     ` Konrad Dybcio
2024-04-18 11:29       ` Dmitry Baryshkov
2024-04-17 20:02 ` [PATCH v2 7/7] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs Konrad Dybcio
2024-04-17 23:49   ` Dmitry Baryshkov
  -- strict thread matches above, loose matches on Subject: below --
2024-06-05 20:10 [PATCH v2 0/7] Add SMEM-based speedbin matching Konrad Dybcio
2024-06-05 20:10 ` [PATCH v2 2/7] soc: qcom: smem: Add a feature code getter Konrad Dybcio

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