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[78.88.45.141]) by smtp.gmail.com with ESMTPSA id xa4-20020a170906fd8400b00a5252e69c7dsm5905590ejb.160.2024.04.17.13.03.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Apr 2024 13:03:17 -0700 (PDT) From: Konrad Dybcio Date: Wed, 17 Apr 2024 22:02:59 +0200 Subject: [PATCH v2 7/7] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240404-topic-smem_speedbin-v2-7-c84f820b7e5b@linaro.org> References: <20240404-topic-smem_speedbin-v2-0-c84f820b7e5b@linaro.org> In-Reply-To: <20240404-topic-smem_speedbin-v2-0-c84f820b7e5b@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713384181; l=2413; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=N9C7J/UXFBbxcLZJ0Wle4it14ExoZJn/aRTDf20iB8I=; b=MHA+uQvVZajZO7HB9yQ9w98lwwxIsrifK11MFrFba+JTdm7p6ywc7iaAOHKu6/NKHBghvMv0k DShJ2TmzIFCDxFEiwF2L/6pAbYWdc5a/F5PivT/SpWn3M5H58jc7ga8 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add the speedbin masks to ensure only the desired OPPs are available on chips of a given bin. Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 5cae8d773cec..2f6842f6a5b7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2087,48 +2087,67 @@ zap-shader { memory-region = <&gpu_micro_code_mem>; }; - /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; + opp-719000000 { + opp-hz = /bits/ 64 <719000000>; + opp-level = ; + opp-supported-hw = <0x1>; + }; + opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-615000000 { opp-hz = /bits/ 64 <615000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-475000000 { opp-hz = /bits/ 64 <475000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-401000000 { opp-hz = /bits/ 64 <401000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-295000000 { opp-hz = /bits/ 64 <295000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-220000000 { opp-hz = /bits/ 64 <220000000>; opp-level = ; + opp-supported-hw = <0x3>; + }; + + opp-124800000 { + opp-hz = /bits/ 64 <124800000>; + opp-level = ; + opp-supported-hw = <0x3>; }; }; }; -- 2.44.0