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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id m20-20020a05600c4f5400b0041632171f51sm1770044wmq.13.2024.04.05.08.59.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 08:59:42 -0700 (PDT) Date: Fri, 5 Apr 2024 17:59:41 +0200 From: Andrew Jones To: Conor Dooley Cc: Max Hsu , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH RFC 02/11] dt-bindings: riscv: Add Sdtrig optional CSRs existence on DT Message-ID: <20240405-ebdb2943657ab08d2d563c03@orel> References: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> <20240329-dev-maxh-lin-452-6-9-v1-2-1534f93b94a7@sifive.com> <20240329-affidavit-anatomist-1118a12c3e60@wendy> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240329-affidavit-anatomist-1118a12c3e60@wendy> On Fri, Mar 29, 2024 at 10:31:10AM +0000, Conor Dooley wrote: > On Fri, Mar 29, 2024 at 05:26:18PM +0800, Max Hsu wrote: > > The mcontext/hcontext/scontext CSRs are optional in the Sdtrig extension, > > to prevent RW operations to the missing CSRs, which will cause > > illegal instructions. > > > > As a solution, we have proposed the dt format for these CSRs. > > As I mentioned in your other patch, I amn't sure what the actual value > is in being told about "sdtrig" itself if so many of the CSRs are > optional. I think we should define pseudo extensions that represent > usable subsets that are allowed by riscv,isa-extensions, such as > those you describe here: sdtrig + mcontext, sdtrig + scontext and > sdtrig + hcontext. Probably also for strig + mscontext. What > additional value does having a debug child node give us that makes > it worth having over something like the above? Yeah, Sdtrig, which doesn't tell you what you get, isn't nice at all. I wonder if we can start with requiring Sdtrig to be accompanied by Ssstrict in order to enable the context CSRs, i.e. Sdtrig - support without optional CSRs Sdtrig+Ssstrict - probe for optional CSRs, support what's found If there are platforms with Sdtrig and optional CSRs, but not Ssstrict, then maybe the optional CSRs can be detected in some vendor-specific way, where the decision as to whether or not that vendor-specific way is acceptable is handled case-by-case. Thanks, drew > > Thanks, > Conor. > > > > > Signed-off-by: Max Hsu > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 18 ++++++++++++++++++ > > 1 file changed, 18 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index d87dd50f1a4b..c713a48c5025 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -137,6 +137,24 @@ properties: > > DMIPS/MHz, relative to highest capacity-dmips-mhz > > in the system. > > > > + debug: > > + type: object > > + properties: > > + compatible: > > + const: riscv,debug-v1.0.0 > > + trigger-module: > > + type: object > > + description: | > > + An indication set of optional CSR existence from > > + riscv-debug-spec Sdtrig extension > > + properties: > > + mcontext-present: > > + type: boolean > > + hcontext-present: > > + type: boolean > > + scontext-present: > > + type: boolean > > + > > anyOf: > > - required: > > - riscv,isa > > > > -- > > 2.43.2 > > > -- > kvm-riscv mailing list > kvm-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/kvm-riscv