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AJvYcCVKDtn7Q/pYGCCZ5ZXSql04GZQuWyHUraBdbc1eeVLEL416N7kv0Fbiq/TO0nZrwz25Cvs/nctY05OctmbisZcLfQoIppVhv4WxtQ== X-Gm-Message-State: AOJu0Yw5sbxAo9UrIEr+cLLfVt3ngTgx6/zpW8h7SFiTbD7MpS96DS98 jW/5acGYEf4Qkd2TOlgG0Ct7micBaA8ABrGxBoAZmwcE2YaM1YVo8hkZ4qxsYQ== X-Google-Smtp-Source: AGHT+IH91S1Z/KeP8j1qCyAsCVGA3WNwVPBN6gvhYhKdgqEwwdwQYimMDHu7d2YE/xvhwIILfPFCUA== X-Received: by 2002:a05:6a21:33a7:b0:1a7:23d1:c30d with SMTP id yy39-20020a056a2133a700b001a723d1c30dmr7748366pzb.8.1712500955282; Sun, 07 Apr 2024 07:42:35 -0700 (PDT) Received: from thinkpad ([120.56.192.184]) by smtp.gmail.com with ESMTPSA id p23-20020aa78617000000b006eab7ca005esm4877624pfn.18.2024.04.07.07.42.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Apr 2024 07:42:34 -0700 (PDT) Date: Sun, 7 Apr 2024 20:12:27 +0530 From: Manivannan Sadhasivam To: Krishna chaitanya chundru Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , johan+linaro@kernel.org, bmasney@redhat.com, djakov@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, vireshk@kernel.org, quic_vbadigan@quicinc.com, quic_skananth@quicinc.com, quic_nitegupt@quicinc.com, quic_parass@quicinc.com, krzysztof.kozlowski@linaro.org Subject: Re: [PATCH v9 3/6] dt-bindings: pci: qcom: Add opp table Message-ID: <20240407144227.GC2679@thinkpad> References: <20240407-opp_support-v9-0-496184dc45d7@quicinc.com> <20240407-opp_support-v9-3-496184dc45d7@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240407-opp_support-v9-3-496184dc45d7@quicinc.com> On Sun, Apr 07, 2024 at 10:07:36AM +0530, Krishna chaitanya chundru wrote: s/opp/OPP > PCIe needs to choose the appropriate performance state of RPMH power s/RPMH/RPMh > domain based upon the PCIe gen speed. > s/upon/on > Adding the Operating Performance Points table allows to adjust power > domain performance state and icc peak bw, depending on the PCIe gen s/icc/ICC s/PCIe gen speed/PCIe data rate > speed and width. > s/width/link width > Signed-off-by: Krishna chaitanya chundru With above changes, Reviewed-by: Manivannan Sadhasivam - Mani > --- > Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml > index 1496d6993ab4..d8c0afaa4b19 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml > @@ -69,6 +69,10 @@ properties: > - const: msi6 > - const: msi7 > > + operating-points-v2: true > + opp-table: > + type: object > + > resets: > maxItems: 1 > > > -- > 2.42.0 > -- மணிவண்ணன் சதாசிவம்