[PATCH v1 1/6] dt-bindings: cache: Document the sifive,perfmon-counters property

Samuel Holland
2024-02-16T00:08:42Z

The SiFive Composable Cache controller contains an optional PMU with a
configurable number of event counters. Document a property which
describes the number of available counters.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 7e8cebe21584..100eda4345de 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -81,6 +81,11 @@ properties:
The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
The reserved memory node should be defined as per the bindings in reserved-memory.txt.

+ sifive,perfmon-counters:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description: Number of PMU counter registers
+
allOf:
- $ref: /schemas/cache-controller.yaml#

--
2.43.0