[PATCH v1 3/6] dt-bindings: cache: Add SiFive Extensible Cache controller

Samuel Holland
2024-02-16T00:08:47Z

From: Eric Lin <eric.lin@sifive.com>

Add YAML DT binding documentation for the SiFive Extensible Cache
controller. The Extensible Cache controller interleaves cache blocks
across a number of heterogeneous independently-programmed slices. Each
slice contains an MMIO interface for configuration, cache maintenance,
error reporting, and performance monitoring.

Signed-off-by: Eric Lin <eric.lin@sifive.com>
Co-developed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

.../cache/sifive,extensiblecache0.yaml | 136 ++++++++++++++++++
1 file changed, 136 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cache/sifive,extensiblecache0.yaml

diff --git a/Documentation/devicetree/bindings/cache/sifive,extensiblecache0.yaml b/Documentation/devicetree/bindings/cache/sifive,extensiblecache0.yaml
new file mode 100644
index 000000000000..d027114dbdba
--- /dev/null
+++ b/Documentation/devicetree/bindings/cache/sifive,extensiblecache0.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2023-2024 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cache/sifive,extensiblecache0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive Extensible Cache Controller
+
+maintainers:
+ - Eric Lin <eric.lin@sifive.com>
+
+description:
+ The SiFive Extensible Cache Controller provides a high-performance extensible
+ system (L2 or L3) cache. It is divided into several independent heterogeneous
+ slices, enabling a flexible topology and physical design.
+
+allOf:
+ - $ref: /schemas/cache-controller.yaml#
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - sifive,extensiblecache0
+
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - const: sifive,extensiblecache0
+ - const: cache
+
+ "#address-cells": true
+ "#size-cells": true
+ ranges: true
+
+ interrupts:
+ maxItems: 1
+
+ cache-block-size:
+ const: 64
+
+ cache-level: true
+ cache-sets: true
+ cache-size: true
+ cache-unified: true
+
+patternProperties:
+ "^cache-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: false
+ properties:
+ reg:
+ maxItems: 1
+
+ cache-block-size:
+ const: 64
+
+ cache-sets: true
+ cache-size: true
+ cache-unified: true
+
+ sifive,bm-event-counters:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description: Number of bucket monitor registers in this slice
+
+ sifive,cache-ways:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Number of ways in this slice (independent of cache size)
+
+ sifive,perfmon-counters:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description: Number of PMU counter registers in this slice
+
+ required:
+ - reg
+ - cache-block-size
+ - cache-sets
+ - cache-size
+ - cache-unified
+ - sifive,cache-ways
+
+required:
+ - compatible
+ - ranges
+ - interrupts
+ - cache-block-size
+ - cache-level
+ - cache-sets
+ - cache-size
+ - cache-unified
+
+additionalProperties: false
+
+examples:
+ - |
+ cache-controller@30040000 {
+ compatible = "sifive,extensiblecache0", "cache";
+ ranges = <0x30040000 0x30040000 0x10000>;
+ interrupts = <0x4>;
+ cache-block-size = <0x40>;
+ cache-level = <3>;
+ cache-sets = <0x800>;
+ cache-size = <0x100000>;
+ cache-unified;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cache-controller@30040000 {
+ reg = <0x30040000 0x4000>;
+ cache-block-size = <0x40>;
+ cache-sets = <0x400>;
+ cache-size = <0x80000>;
+ cache-unified;
+ sifive,bm-event-counters = <8>;
+ sifive,cache-ways = <9>;
+ sifive,perfmon-counters = <8>;
+ };
+
+ cache-controller@30044000 {
+ reg = <0x30044000 0x4000>;
+ cache-block-size = <0x40>;
+ cache-sets = <0x400>;
+ cache-size = <0x80000>;
+ cache-unified;
+ sifive,bm-event-counters = <8>;
+ sifive,cache-ways = <9>;
+ sifive,perfmon-counters = <8>;
+ };
+ };
--
2.43.0